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hv: fix bug in some embedded assembly code in vmx

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The patch fixes the issue when SOS can't boot using HV release version.

In current code, the assembly code for "sgdt" & "sidt" is not right.
The operand is output, not input.

Also, current code use "rdmsr" instruction to read MSR_IA32_SYSENTER_CS,
which doesn't sepcify the clobbered registers it uses.
This patch uses API msr_read to read MSR_IA32_SYSENTER_CS.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Binbin Wu 2018-07-11 16:26:21 +08:00 committed by Jack Ren
parent 83361018b5
commit b4fb261b18
1 changed files with 6 additions and 10 deletions
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16
hypervisor/arch/x86/vmx.c
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@ -702,7 +702,7 @@ static void init_guest_state(struct vcpu *vcpu)
/* Base *//* TODO: Should guest GDTB point to host GDTB ? */ /* Base *//* TODO: Should guest GDTB point to host GDTB ? */
/* Obtain the current global descriptor table base */ /* Obtain the current global descriptor table base */
asm volatile ("sgdt %0" : : "m" (gdtb)); asm volatile ("sgdt %0" : "=m"(gdtb)::"memory");
value32 = gdtb.limit; value32 = gdtb.limit;
@ -737,7 +737,7 @@ static void init_guest_state(struct vcpu *vcpu)
descriptor_table idtb = {0, 0}; descriptor_table idtb = {0, 0};
/* TODO: Should guest IDTR point to host IDTR ? */ /* TODO: Should guest IDTR point to host IDTR ? */
asm volatile ("sidt %0"::"m" (idtb)); asm volatile ("sidt %0":"=m"(idtb)::"memory");
/* Limit */ /* Limit */
limit = idtb.limit; limit = idtb.limit;
@ -935,9 +935,7 @@ static void init_guest_state(struct vcpu *vcpu)
exec_vmwrite(field, value32); exec_vmwrite(field, value32);
pr_dbg("VMX_GUEST_SMBASE: 0x%x ", value32); pr_dbg("VMX_GUEST_SMBASE: 0x%x ", value32);
asm volatile ("mov $0x174, %rcx"); value32 = msr_read(MSR_IA32_SYSENTER_CS) & 0xFFFFFFFFU;
asm volatile ("rdmsr");
asm volatile ("mov %%rax, %0"::"m" (value32):"memory");
field = VMX_GUEST_IA32_SYSENTER_CS; field = VMX_GUEST_IA32_SYSENTER_CS;
exec_vmwrite(field, value32); exec_vmwrite(field, value32);
pr_dbg("VMX_GUEST_IA32_SYSENTER_CS: 0x%x ", pr_dbg("VMX_GUEST_IA32_SYSENTER_CS: 0x%x ",
@ -1045,7 +1043,7 @@ static void init_host_state(__unused struct vcpu *vcpu)
/* TODO: Should guest GDTB point to host GDTB ? */ /* TODO: Should guest GDTB point to host GDTB ? */
/* Obtain the current global descriptor table base */ /* Obtain the current global descriptor table base */
asm volatile ("sgdt %0"::"m" (gdtb)); asm volatile ("sgdt %0":"=m"(gdtb)::"memory");
value32 = gdtb.limit; value32 = gdtb.limit;
if (((gdtb.base >> 47) & 0x1UL) != 0UL) if (((gdtb.base >> 47) & 0x1UL) != 0UL)
@ -1082,7 +1080,7 @@ static void init_host_state(__unused struct vcpu *vcpu)
pr_dbg("VMX_HOST_TR_BASE: 0x%x ", realtrbase); pr_dbg("VMX_HOST_TR_BASE: 0x%x ", realtrbase);
/* Obtain the current interrupt descriptor table base */ /* Obtain the current interrupt descriptor table base */
asm volatile ("sidt %0"::"m" (idtb)); asm volatile ("sidt %0":"=m"(idtb)::"memory");
/* base */ /* base */
if (((idtb.base >> 47) & 0x1UL) != 0UL) if (((idtb.base >> 47) & 0x1UL) != 0UL)
idtb.base |= 0xffff000000000000UL; idtb.base |= 0xffff000000000000UL;
@ -1091,9 +1089,7 @@ static void init_host_state(__unused struct vcpu *vcpu)
exec_vmwrite(field, idtb.base); exec_vmwrite(field, idtb.base);
pr_dbg("VMX_HOST_IDTR_BASE: 0x%x ", idtb.base); pr_dbg("VMX_HOST_IDTR_BASE: 0x%x ", idtb.base);
asm volatile ("mov $0x174, %rcx"); value32 = msr_read(MSR_IA32_SYSENTER_CS) & 0xFFFFFFFFU;
asm volatile ("rdmsr");
asm volatile ("mov %%rax, %0"::"m" (value32):"memory");
field = VMX_HOST_IA32_SYSENTER_CS; field = VMX_HOST_IA32_SYSENTER_CS;
exec_vmwrite(field, value32); exec_vmwrite(field, value32);
pr_dbg("VMX_HOST_IA32_SYSENTER_CS: 0x%x ", pr_dbg("VMX_HOST_IA32_SYSENTER_CS: 0x%x ",