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hv: pci: check whether a PCI device is host bridge or not by class

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According PCI Code and ID Assignment Specification Revision 1.11, a PCI device
whose Base Class is 06h and Sub-Class is 00h is a Host bridge.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Li Fei1
2020-06-02 09:27:40 +08:00
committed by wenlingz
parent 0bd2daf1c5
commit b8f151a55f
6 changed files with 29 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hypervisor/include/arch/x86/pci_dev.h
View File

@@ -9,8 +9,6 @@
#include <vm_config.h>
#define SOS_EMULATED_PCI_DEV_NUM 1U
extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
struct pci_pdev;

2
hypervisor/include/arch/x86/vm_config.h
View File

@@ -36,7 +36,7 @@
#define CONFIG_SOS_VM .load_order = SOS_VM, \
.uuid = SOS_VM_UUID, \
.severity = SEVERITY_SOS, \
.pci_dev_num = SOS_EMULATED_PCI_DEV_NUM, \
.pci_dev_num = 0U, \
.pci_devs = sos_pci_devs
#define CONFIG_SAFETY_VM(idx) .load_order = PRE_LAUNCHED_VM, \

12
hypervisor/include/hw/pci.h
View File

@@ -223,6 +223,8 @@ struct pci_sriov_cap {
struct pci_pdev {
uint8_t hdr_type;
uint8_t base_class;
uint8_t sub_class;
/* IOMMU responsible for DMA and Interrupt Remapping for this device */
uint32_t drhd_index;
@@ -250,6 +252,16 @@ struct pci_cfg_ops {
void (*pci_write_cfg)(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
};
static inline bool is_host_bridge(const struct pci_pdev *pdev)
{
return (pdev->base_class == PCIC_BRIDGE) && (pdev->sub_class == PCIS_BRIDGE_HOST);
}
static inline bool is_bridge(const struct pci_pdev *pdev)
{
return pdev->hdr_type == PCIM_HDRTYPE_BRIDGE;
}
static inline uint32_t pci_bar_offset(uint32_t idx)
{
return PCIR_BARS + (idx << 2U);