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hv: pci: check whether a PCI device is host bridge or not by class

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According PCI Code and ID Assignment Specification Revision 1.11, a PCI device
whose Base Class is 06h and Sub-Class is 00h is a Host bridge.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Li Fei1 2020-06-02 09:27:40 +08:00 committed by wenlingz
parent 0bd2daf1c5
commit b8f151a55f
6 changed files with 29 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
hypervisor/arch/x86/configs/pci_dev.c
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@ -9,13 +9,7 @@
#include <pci_dev.h> #include <pci_dev.h>
#include <vpci.h> #include <vpci.h>
struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM] = { struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
{
.emu_type = PCI_DEV_TYPE_HVEMUL,
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U},
.vdev_ops = &vhostbridge_ops,
},
};
/* /*
* @pre pdev != NULL; * @pre pdev != NULL;
@ -28,12 +22,9 @@ static bool is_allocated_to_prelaunched_vm(struct pci_pdev *pdev)
struct acrn_vm_config *vm_config; struct acrn_vm_config *vm_config;
struct acrn_vm_pci_dev_config *dev_config; struct acrn_vm_pci_dev_config *dev_config;
for (vmid = 0U; vmid < CONFIG_MAX_VM_NUM; vmid++) { for (vmid = 0U; (vmid < CONFIG_MAX_VM_NUM) && !found; vmid++) {
vm_config = get_vm_config(vmid); vm_config = get_vm_config(vmid);
if (vm_config->load_order != PRE_LAUNCHED_VM) { if (vm_config->load_order == PRE_LAUNCHED_VM) {
continue;
}
for (pci_idx = 0U; pci_idx < vm_config->pci_dev_num; pci_idx++) { for (pci_idx = 0U; pci_idx < vm_config->pci_dev_num; pci_idx++) {
dev_config = &vm_config->pci_devs[pci_idx]; dev_config = &vm_config->pci_devs[pci_idx];
if ((dev_config->emu_type == PCI_DEV_TYPE_PTDEV) && if ((dev_config->emu_type == PCI_DEV_TYPE_PTDEV) &&
@ -43,9 +34,6 @@ static bool is_allocated_to_prelaunched_vm(struct pci_pdev *pdev)
break; break;
} }
} }
if (found) {
break;
} }
} }

4
hypervisor/dm/vpci/vpci.c
View File

@ -624,8 +624,10 @@ struct pci_vdev *vpci_init_vdev(struct acrn_vpci *vpci, struct acrn_vm_pci_dev_c
if (dev_config->vdev_ops != NULL) { if (dev_config->vdev_ops != NULL) {
vdev->vdev_ops = dev_config->vdev_ops; vdev->vdev_ops = dev_config->vdev_ops;
} else { } else {
if (vdev->pdev->hdr_type == PCIM_HDRTYPE_BRIDGE) { if (is_bridge(vdev->pdev)) {
vdev->vdev_ops = &vpci_bridge_ops; vdev->vdev_ops = &vpci_bridge_ops;
} else if (is_host_bridge(vdev->pdev)) {
vdev->vdev_ops = &vhostbridge_ops;
} else { } else {
vdev->vdev_ops = &pci_pt_dev_ops; vdev->vdev_ops = &pci_pt_dev_ops;
} }

2
hypervisor/hw/pci.c
View File

@ -760,6 +760,8 @@ struct pci_pdev *init_pdev(uint16_t pbdf, uint32_t drhd_index)
pdev = &pci_pdev_array[num_pci_pdev]; pdev = &pci_pdev_array[num_pci_pdev];
pdev->bdf.value = pbdf; pdev->bdf.value = pbdf;
pdev->hdr_type = hdr_type; pdev->hdr_type = hdr_type;
pdev->base_class = (uint8_t)pci_pdev_read_cfg(bdf, PCIR_CLASS, 1U);
pdev->sub_class = (uint8_t)pci_pdev_read_cfg(bdf, PCIR_SUBCLASS, 1U);
pdev->nr_bars = pci_pdev_get_nr_bars(hdr_type); pdev->nr_bars = pci_pdev_get_nr_bars(hdr_type);
if (hdr_type == PCIM_HDRTYPE_NORMAL) { if (hdr_type == PCIM_HDRTYPE_NORMAL) {
pdev_save_bar(pdev); pdev_save_bar(pdev);

2
hypervisor/include/arch/x86/pci_dev.h
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@ -9,8 +9,6 @@
#include <vm_config.h> #include <vm_config.h>
#define SOS_EMULATED_PCI_DEV_NUM 1U
extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM]; extern struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
struct pci_pdev; struct pci_pdev;

2
hypervisor/include/arch/x86/vm_config.h
View File

@ -36,7 +36,7 @@
#define CONFIG_SOS_VM .load_order = SOS_VM, \ #define CONFIG_SOS_VM .load_order = SOS_VM, \
.uuid = SOS_VM_UUID, \ .uuid = SOS_VM_UUID, \
.severity = SEVERITY_SOS, \ .severity = SEVERITY_SOS, \
.pci_dev_num = SOS_EMULATED_PCI_DEV_NUM, \ .pci_dev_num = 0U, \
.pci_devs = sos_pci_devs .pci_devs = sos_pci_devs
#define CONFIG_SAFETY_VM(idx) .load_order = PRE_LAUNCHED_VM, \ #define CONFIG_SAFETY_VM(idx) .load_order = PRE_LAUNCHED_VM, \

12
hypervisor/include/hw/pci.h
View File

@ -223,6 +223,8 @@ struct pci_sriov_cap {
struct pci_pdev { struct pci_pdev {
uint8_t hdr_type; uint8_t hdr_type;
uint8_t base_class;
uint8_t sub_class;
/* IOMMU responsible for DMA and Interrupt Remapping for this device */ /* IOMMU responsible for DMA and Interrupt Remapping for this device */
uint32_t drhd_index; uint32_t drhd_index;
@ -250,6 +252,16 @@ struct pci_cfg_ops {
void (*pci_write_cfg)(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val); void (*pci_write_cfg)(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
}; };
static inline bool is_host_bridge(const struct pci_pdev *pdev)
{
return (pdev->base_class == PCIC_BRIDGE) && (pdev->sub_class == PCIS_BRIDGE_HOST);
}
static inline bool is_bridge(const struct pci_pdev *pdev)
{
return pdev->hdr_type == PCIM_HDRTYPE_BRIDGE;
}
static inline uint32_t pci_bar_offset(uint32_t idx) static inline uint32_t pci_bar_offset(uint32_t idx)
{ {
return PCIR_BARS + (idx << 2U); return PCIR_BARS + (idx << 2U);