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hv: rename the ACRN_DBG_XXX

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Refine this MACRO 'ACRN_DBG_XXX' to 'DBG_LEVEL_XXX'

Tracked-On: #4348
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Yonghua Huang
2020-01-09 16:14:23 +08:00
committed by wenlingz
parent 03f5c639a0
commit b90862921e
23 changed files with 227 additions and 230 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
hypervisor/dm/io_req.c
View File

@@ -8,7 +8,7 @@
#include <errno.h>
#include <logmsg.h>
#define ACRN_DBG_IOREQUEST 6U
#define DBG_LEVEL_IOREQ 6U
static uint32_t acrn_vhm_notification_vector = VECTOR_HYPERVISOR_CALLBACK_VHM;
#define MMIO_DEFAULT_VALUE_SIZE_1 (0xFFUL)
@@ -21,8 +21,8 @@ __unused static void acrn_print_request(uint16_t vcpu_id, const struct vhm_reque
{
switch (req->type) {
case REQ_MMIO:
dev_dbg(ACRN_DBG_IOREQUEST, "[vcpu_id=%hu type=MMIO]", vcpu_id);
dev_dbg(ACRN_DBG_IOREQUEST,
dev_dbg(DBG_LEVEL_IOREQ, "[vcpu_id=%hu type=MMIO]", vcpu_id);
dev_dbg(DBG_LEVEL_IOREQ,
"gpa=0x%lx, R/W=%d, size=%ld value=0x%lx processed=%lx",
req->reqs.mmio.address,
req->reqs.mmio.direction,
@@ -31,8 +31,8 @@ __unused static void acrn_print_request(uint16_t vcpu_id, const struct vhm_reque
req->processed);
break;
case REQ_PORTIO:
dev_dbg(ACRN_DBG_IOREQUEST, "[vcpu_id=%hu type=PORTIO]", vcpu_id);
dev_dbg(ACRN_DBG_IOREQUEST,
dev_dbg(DBG_LEVEL_IOREQ, "[vcpu_id=%hu type=PORTIO]", vcpu_id);
dev_dbg(DBG_LEVEL_IOREQ,
"IO=0x%lx, R/W=%d, size=%ld value=0x%lx processed=%lx",
req->reqs.pio.address,
req->reqs.pio.direction,
@@ -41,7 +41,7 @@ __unused static void acrn_print_request(uint16_t vcpu_id, const struct vhm_reque
req->processed);
break;
default:
dev_dbg(ACRN_DBG_IOREQUEST, "[vcpu_id=%hu type=%d] NOT support type",
dev_dbg(DBG_LEVEL_IOREQ, "[vcpu_id=%hu type=%d] NOT support type",
vcpu_id, req->type);
break;
}

16
hypervisor/dm/vioapic.c
View File

@@ -39,7 +39,7 @@
#define RTBL_RO_BITS ((uint32_t)0x00004000U | (uint32_t)0x00001000U) /*Remote IRR and Delivery Status bits*/
#define ACRN_DBG_IOAPIC 6U
#define DBG_LEVEL_VIOAPIC 6U
#define ACRN_IOAPIC_VERSION 0x11U
#define IOAPIC_ID_MASK 0x0f000000U
@@ -63,7 +63,7 @@ vioapic_generate_intr(struct acrn_vioapic *vioapic, uint32_t pin)
rte = vioapic->rtbl[pin];
if (rte.bits.intr_mask == IOAPIC_RTE_MASK_SET) {
dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: masked", pin);
dev_dbg(DBG_LEVEL_VIOAPIC, "ioapic pin%hhu: masked", pin);
} else {
phys = (rte.bits.dest_mode == IOAPIC_RTE_DESTMODE_PHY);
delmode = rte.bits.delivery_mode;
@@ -310,7 +310,7 @@ static void vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr,
if ((vioapic->vm->wire_mode == VPIC_WIRE_NULL) ||
(vioapic->vm->wire_mode == VPIC_WIRE_INTR)) {
vioapic->vm->wire_mode = VPIC_WIRE_IOAPIC;
dev_dbg(ACRN_DBG_IOAPIC, "vpic wire mode -> IOAPIC");
dev_dbg(DBG_LEVEL_VIOAPIC, "vpic wire mode -> IOAPIC");
} else {
pr_err("WARNING: invalid vpic wire mode change");
wire_mode_valid = false;
@@ -319,14 +319,14 @@ static void vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr,
} else {
if (vioapic->vm->wire_mode == VPIC_WIRE_IOAPIC) {
vioapic->vm->wire_mode = VPIC_WIRE_INTR;
dev_dbg(ACRN_DBG_IOAPIC, "vpic wire mode -> INTR");
dev_dbg(DBG_LEVEL_VIOAPIC, "vpic wire mode -> INTR");
}
}
}
if (wire_mode_valid) {
vioapic->rtbl[pin] = new;
dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: redir table entry %#lx",
dev_dbg(DBG_LEVEL_VIOAPIC, "ioapic pin%hhu: redir table entry %#lx",
pin, vioapic->rtbl[pin].full);
/* remap for ptdev */
@@ -345,7 +345,7 @@ static void vioapic_indirect_write(struct acrn_vioapic *vioapic, uint32_t addr,
if ((vioapic->rtbl[pin].bits.intr_mask == IOAPIC_RTE_MASK_CLR) &&
(vioapic->rtbl[pin].bits.remote_irr == 0UL) &&
vioapic_need_intr(vioapic, (uint16_t)pin)) {
dev_dbg(ACRN_DBG_IOAPIC, "ioapic pin%hhu: asserted at rtbl write", pin);
dev_dbg(DBG_LEVEL_VIOAPIC, "ioapic pin%hhu: asserted at rtbl write", pin);
vioapic_generate_intr(vioapic, pin);
}
}
@@ -410,7 +410,7 @@ vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector)
}
vioapic = vm_ioapic(vm);
dev_dbg(ACRN_DBG_IOAPIC, "ioapic processing eoi for vector %u", vector);
dev_dbg(DBG_LEVEL_VIOAPIC, "ioapic processing eoi for vector %u", vector);
/* notify device to ack if assigned pin */
for (pin = 0U; pin < pincount; pin++) {
@@ -437,7 +437,7 @@ vioapic_process_eoi(struct acrn_vm *vm, uint32_t vector)
vioapic->rtbl[pin].bits.remote_irr = 0U;
if (vioapic_need_intr(vioapic, (uint16_t)pin)) {
dev_dbg(ACRN_DBG_IOAPIC,
dev_dbg(DBG_LEVEL_VIOAPIC,
"ioapic pin%hhu: asserted at eoi", pin);
vioapic_generate_intr(vioapic, pin);
}

42
hypervisor/dm/vpic.c
View File

@@ -33,7 +33,7 @@
#include <spinlock.h>
#include <logmsg.h>
#define ACRN_DBG_PIC 6U
#define DBG_LEVEL_PIC 6U
static void vpic_set_pinstate(struct acrn_vpic *vpic, uint32_t pin, uint8_t level);
@@ -149,7 +149,7 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
i8259 = &vpic->i8259[1];
pin = vpic_get_highest_irrpin(i8259);
if (!i8259->intr_raised && (pin < NR_VPIC_PINS_PER_CHIP)) {
dev_dbg(ACRN_DBG_PIC,
dev_dbg(DBG_LEVEL_PIC,
"pic slave notify pin = %hhu (imr 0x%x irr 0x%x isr 0x%x)\n",
pin, i8259->mask, i8259->request, i8259->service);
@@ -160,7 +160,7 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
vpic_set_pinstate(vpic, 2U, 1U);
vpic_set_pinstate(vpic, 2U, 0U);
} else {
dev_dbg(ACRN_DBG_PIC,
dev_dbg(DBG_LEVEL_PIC,
"pic slave no eligible interrupt (imr 0x%x irr 0x%x isr 0x%x)",
i8259->mask, i8259->request, i8259->service);
}
@@ -171,7 +171,7 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
i8259 = &vpic->i8259[0];
pin = vpic_get_highest_irrpin(i8259);
if (!i8259->intr_raised && (pin < NR_VPIC_PINS_PER_CHIP)) {
dev_dbg(ACRN_DBG_PIC,
dev_dbg(DBG_LEVEL_PIC,
"pic master notify pin = %hhu (imr 0x%x irr 0x%x isr 0x%x)\n",
pin, i8259->mask, i8259->request, i8259->service);
@@ -218,7 +218,7 @@ static void vpic_notify_intr(struct acrn_vpic *vpic)
vioapic_set_irqline_lock(vpic->vm, 0U, GSI_RAISING_PULSE);
}
} else {
dev_dbg(ACRN_DBG_PIC,
dev_dbg(DBG_LEVEL_PIC,
"pic master no eligible interrupt (imr 0x%x irr 0x%x isr 0x%x)",
i8259->mask, i8259->request, i8259->service);
}
@@ -228,7 +228,7 @@ static int32_t vpic_icw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i
{
int32_t ret;
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw1 0x%x\n",
dev_dbg(DBG_LEVEL_PIC, "vm 0x%x: i8259 icw1 0x%x\n",
vpic->vm, val);
i8259->ready = false;
@@ -242,10 +242,10 @@ static int32_t vpic_icw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i
i8259->smm = 0U;
if ((val & ICW1_SNGL) != 0U) {
dev_dbg(ACRN_DBG_PIC, "vpic cascade mode required\n");
dev_dbg(DBG_LEVEL_PIC, "vpic cascade mode required\n");
ret = -1;
} else if ((val & ICW1_IC4) == 0U) {
dev_dbg(ACRN_DBG_PIC, "vpic icw4 required\n");
dev_dbg(DBG_LEVEL_PIC, "vpic icw4 required\n");
ret = -1;
} else {
i8259->icw_num++;
@@ -257,7 +257,7 @@ static int32_t vpic_icw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i
static int32_t vpic_icw2(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
{
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw2 0x%x\n",
dev_dbg(DBG_LEVEL_PIC, "vm 0x%x: i8259 icw2 0x%x\n",
vpic->vm, val);
i8259->irq_base = val & 0xf8U;
@@ -269,7 +269,7 @@ static int32_t vpic_icw2(const struct acrn_vpic *vpic, struct i8259_reg_state *i
static int32_t vpic_icw3(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
{
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw3 0x%x\n",
dev_dbg(DBG_LEVEL_PIC, "vm 0x%x: i8259 icw3 0x%x\n",
vpic->vm, val);
i8259->icw_num++;
@@ -281,11 +281,11 @@ static int32_t vpic_icw4(const struct acrn_vpic *vpic, struct i8259_reg_state *i
{
int32_t ret;
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 icw4 0x%x\n",
dev_dbg(DBG_LEVEL_PIC, "vm 0x%x: i8259 icw4 0x%x\n",
vpic->vm, val);
if ((val & ICW4_8086) == 0U) {
dev_dbg(ACRN_DBG_PIC,
dev_dbg(DBG_LEVEL_PIC,
"vpic microprocessor mode required\n");
ret = -1;
} else {
@@ -297,7 +297,7 @@ static int32_t vpic_icw4(const struct acrn_vpic *vpic, struct i8259_reg_state *i
if (master_pic(vpic, i8259)) {
i8259->sfn = true;
} else {
dev_dbg(ACRN_DBG_PIC,
dev_dbg(DBG_LEVEL_PIC,
"Ignoring special fully nested mode on slave pic: %#x",
val);
}
@@ -316,7 +316,7 @@ static int32_t vpic_ocw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i
uint32_t pin, i, bit;
uint8_t old = i8259->mask;
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 ocw1 0x%x\n",
dev_dbg(DBG_LEVEL_PIC, "vm 0x%x: i8259 ocw1 0x%x\n",
vpic->vm, val);
i8259->mask = val & 0xffU;
@@ -352,7 +352,7 @@ static int32_t vpic_ocw1(const struct acrn_vpic *vpic, struct i8259_reg_state *i
static int32_t vpic_ocw2(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
{
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 ocw2 0x%x\n",
dev_dbg(DBG_LEVEL_PIC, "vm 0x%x: i8259 ocw2 0x%x\n",
vpic->vm, val);
i8259->rotate = ((val & OCW2_R) != 0U);
@@ -393,12 +393,12 @@ static int32_t vpic_ocw2(const struct acrn_vpic *vpic, struct i8259_reg_state *i
static int32_t vpic_ocw3(const struct acrn_vpic *vpic, struct i8259_reg_state *i8259, uint8_t val)
{
dev_dbg(ACRN_DBG_PIC, "vm 0x%x: i8259 ocw3 0x%x\n",
dev_dbg(DBG_LEVEL_PIC, "vm 0x%x: i8259 ocw3 0x%x\n",
vpic->vm, val);
if ((val & OCW3_ESMM) != 0U) {
i8259->smm = ((val & OCW3_SMM) != 0U) ? 1U : 0U;
dev_dbg(ACRN_DBG_PIC, "%s i8259 special mask mode %s\n",
dev_dbg(DBG_LEVEL_PIC, "%s i8259 special mask mode %s\n",
master_pic(vpic, i8259) ? "master" : "slave",
(i8259->smm != 0U) ? "enabled" : "disabled");
}
@@ -436,16 +436,16 @@ static void vpic_set_pinstate(struct acrn_vpic *vpic, uint32_t pin, uint8_t leve
if (((old_lvl == 0U) && (level == 1U)) || ((level == 1U) && lvl_trigger)) {
/* raising edge or level */
dev_dbg(ACRN_DBG_PIC, "pic pin%hhu: asserted\n", pin);
dev_dbg(DBG_LEVEL_PIC, "pic pin%hhu: asserted\n", pin);
i8259->request |= (uint8_t)(1U << (pin & 0x7U));
} else if ((old_lvl == 1U) && (level == 0U)) {
/* falling edge */
dev_dbg(ACRN_DBG_PIC, "pic pin%hhu: deasserted\n", pin);
dev_dbg(DBG_LEVEL_PIC, "pic pin%hhu: deasserted\n", pin);
if (lvl_trigger) {
i8259->request &= ~(uint8_t)(1U << (pin & 0x7U));
}
} else {
dev_dbg(ACRN_DBG_PIC, "pic pin%hhu: %s, ignored\n",
dev_dbg(DBG_LEVEL_PIC, "pic pin%hhu: %s, ignored\n",
pin, (level != 0U) ? "asserted" : "deasserted");
}
}
@@ -555,7 +555,7 @@ void vpic_pending_intr(struct acrn_vpic *vpic, uint32_t *vecptr)
} else {
*vecptr = i8259->irq_base + pin;
dev_dbg(ACRN_DBG_PIC, "Got pending vector 0x%x\n", *vecptr);
dev_dbg(DBG_LEVEL_PIC, "Got pending vector 0x%x\n", *vecptr);
}
spinlock_release(&(vpic->lock));