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hv: add struct acrn_vcpu_regs
Add struct acrn_vcpu_regs and make struct boot_ctx based on struct acrn_vcpu_regs. vm0_boot_context is also changed from struct boot_ctx to struct acrn_vcpu_regs. Tracked-On: #1231 Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
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@@ -8,70 +8,86 @@
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#define VM0_BOOT_H
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#ifdef ASSEMBLER
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#define BOOT_CTX_CR0_OFFSET 0
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#define BOOT_CTX_CR3_OFFSET 8
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#define BOOT_CTX_CR4_OFFSET 16
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#define BOOT_CTX_IDT_OFFSET 24
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#define BOOT_CTX_GDT_OFFSET 34
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#define BOOT_CTX_LDT_SEL_OFFSET 44
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#define BOOT_CTX_TR_SEL_OFFSET 46
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#define BOOT_CTX_CS_SEL_OFFSET 48
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#define BOOT_CTX_SS_SEL_OFFSET 50
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#define BOOT_CTX_DS_SEL_OFFSET 52
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#define BOOT_CTX_ES_SEL_OFFSET 54
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#define BOOT_CTX_FS_SEL_OFFSET 56
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#define BOOT_CTX_GS_SEL_OFFSET 58
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#define BOOT_CTX_CS_AR_OFFSET 60
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#define BOOT_CTX_EFER_LOW_OFFSET 64
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#define BOOT_CTX_EFER_HIGH_OFFSET 68
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#define BOOT_CTX_CR0_OFFSET 176
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#define BOOT_CTX_CR3_OFFSET 192
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#define BOOT_CTX_CR4_OFFSET 184
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#define BOOT_CTX_IDT_OFFSET 144
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#define BOOT_CTX_GDT_OFFSET 128
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#define BOOT_CTX_LDT_SEL_OFFSET 280
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#define BOOT_CTX_TR_SEL_OFFSET 282
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#define BOOT_CTX_CS_SEL_OFFSET 268
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#define BOOT_CTX_SS_SEL_OFFSET 270
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#define BOOT_CTX_DS_SEL_OFFSET 272
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#define BOOT_CTX_ES_SEL_OFFSET 274
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#define BOOT_CTX_FS_SEL_OFFSET 276
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#define BOOT_CTX_GS_SEL_OFFSET 278
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#define BOOT_CTX_CS_AR_OFFSET 248
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#define BOOT_CTX_EFER_LOW_OFFSET 200
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#define BOOT_CTX_EFER_HIGH_OFFSET 204
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#define SIZE_OF_BOOT_CTX 296
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#else
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#include <gpr.h>
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#define BOOT_CTX_CR0_OFFSET 0U
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#define BOOT_CTX_CR3_OFFSET 8U
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#define BOOT_CTX_CR4_OFFSET 16U
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#define BOOT_CTX_IDT_OFFSET 24U
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#define BOOT_CTX_GDT_OFFSET 34U
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#define BOOT_CTX_LDT_SEL_OFFSET 44U
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#define BOOT_CTX_TR_SEL_OFFSET 46U
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#define BOOT_CTX_CS_SEL_OFFSET 48U
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#define BOOT_CTX_SS_SEL_OFFSET 50U
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#define BOOT_CTX_DS_SEL_OFFSET 52U
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#define BOOT_CTX_ES_SEL_OFFSET 54U
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#define BOOT_CTX_FS_SEL_OFFSET 56U
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#define BOOT_CTX_GS_SEL_OFFSET 58U
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#define BOOT_CTX_CS_AR_OFFSET 60U
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#define BOOT_CTX_EFER_LOW_OFFSET 64U
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#define BOOT_CTX_EFER_HIGH_OFFSET 68U
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#define BOOT_CTX_CR0_OFFSET 176U
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#define BOOT_CTX_CR3_OFFSET 192U
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#define BOOT_CTX_CR4_OFFSET 184U
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#define BOOT_CTX_IDT_OFFSET 144U
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#define BOOT_CTX_GDT_OFFSET 128U
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#define BOOT_CTX_LDT_SEL_OFFSET 280U
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#define BOOT_CTX_TR_SEL_OFFSET 282U
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#define BOOT_CTX_CS_SEL_OFFSET 268U
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#define BOOT_CTX_SS_SEL_OFFSET 270U
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#define BOOT_CTX_DS_SEL_OFFSET 272U
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#define BOOT_CTX_ES_SEL_OFFSET 274U
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#define BOOT_CTX_FS_SEL_OFFSET 276U
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#define BOOT_CTX_GS_SEL_OFFSET 278U
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#define BOOT_CTX_CS_AR_OFFSET 248U
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#define BOOT_CTX_EFER_LOW_OFFSET 200U
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#define BOOT_CTX_EFER_HIGH_OFFSET 204U
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#define SIZE_OF_BOOT_CTX 296U
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struct dt_addr {
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/* struct to define how the descriptor stored in memory.
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* Refer SDM Vol3 3.5.1 "Segment Descriptor Tables"
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* Figure 3-11
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*/
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struct acrn_descriptor_ptr {
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uint16_t limit;
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uint64_t base;
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uint16_t reserved[3]; /* align struct size to 64bit */
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} __attribute__((packed));
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struct boot_ctx {
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uint64_t cr0;
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uint64_t cr3;
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uint64_t cr4;
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struct dt_addr idt;
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struct dt_addr gdt;
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uint16_t ldt_sel;
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uint16_t tr_sel;
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/* align the order to ext_context */
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uint16_t cs_sel;
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uint16_t ss_sel;
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uint16_t ds_sel;
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uint16_t es_sel;
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uint16_t fs_sel;
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uint16_t gs_sel;
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uint32_t cs_ar;
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uint64_t ia32_efer;
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#ifdef CONFIG_EFI_STUB
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struct acrn_vcpu_regs {
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struct acrn_gp_regs gprs;
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uint64_t rip;
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uint64_t rflags;
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struct acrn_descriptor_ptr gdt;
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struct acrn_descriptor_ptr idt;
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uint64_t rip;
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uint64_t cs_base;
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uint64_t cr0;
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uint64_t cr4;
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uint64_t cr3;
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uint64_t ia32_efer;
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uint64_t rflags;
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uint64_t reserved_64[4];
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uint32_t cs_ar;
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uint32_t reserved_32[4];
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/* don't change the order of following sel */
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uint16_t cs_sel;
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uint16_t ss_sel;
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uint16_t ds_sel;
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uint16_t es_sel;
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uint16_t fs_sel;
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uint16_t gs_sel;
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uint16_t ldt_sel;
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uint16_t tr_sel;
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uint16_t reserved_16[4];
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};
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struct boot_ctx {
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struct acrn_vcpu_regs vcpu_regs;
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#ifdef CONFIG_EFI_STUB
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void *rsdp;
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void *ap_trampoline_buf;
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#endif
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