hv: add struct acrn_vcpu_regs

Add struct acrn_vcpu_regs and make struct boot_ctx based on
struct acrn_vcpu_regs.

vm0_boot_context is also changed from struct boot_ctx to struct
acrn_vcpu_regs.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
This commit is contained in:
Yin Fengwei
2018-09-28 14:36:53 +08:00
committed by lijinxia
parent 843f7721f0
commit ba1aa40707
5 changed files with 98 additions and 80 deletions

View File

@@ -8,70 +8,86 @@
#define VM0_BOOT_H
#ifdef ASSEMBLER
#define BOOT_CTX_CR0_OFFSET 0
#define BOOT_CTX_CR3_OFFSET 8
#define BOOT_CTX_CR4_OFFSET 16
#define BOOT_CTX_IDT_OFFSET 24
#define BOOT_CTX_GDT_OFFSET 34
#define BOOT_CTX_LDT_SEL_OFFSET 44
#define BOOT_CTX_TR_SEL_OFFSET 46
#define BOOT_CTX_CS_SEL_OFFSET 48
#define BOOT_CTX_SS_SEL_OFFSET 50
#define BOOT_CTX_DS_SEL_OFFSET 52
#define BOOT_CTX_ES_SEL_OFFSET 54
#define BOOT_CTX_FS_SEL_OFFSET 56
#define BOOT_CTX_GS_SEL_OFFSET 58
#define BOOT_CTX_CS_AR_OFFSET 60
#define BOOT_CTX_EFER_LOW_OFFSET 64
#define BOOT_CTX_EFER_HIGH_OFFSET 68
#define BOOT_CTX_CR0_OFFSET 176
#define BOOT_CTX_CR3_OFFSET 192
#define BOOT_CTX_CR4_OFFSET 184
#define BOOT_CTX_IDT_OFFSET 144
#define BOOT_CTX_GDT_OFFSET 128
#define BOOT_CTX_LDT_SEL_OFFSET 280
#define BOOT_CTX_TR_SEL_OFFSET 282
#define BOOT_CTX_CS_SEL_OFFSET 268
#define BOOT_CTX_SS_SEL_OFFSET 270
#define BOOT_CTX_DS_SEL_OFFSET 272
#define BOOT_CTX_ES_SEL_OFFSET 274
#define BOOT_CTX_FS_SEL_OFFSET 276
#define BOOT_CTX_GS_SEL_OFFSET 278
#define BOOT_CTX_CS_AR_OFFSET 248
#define BOOT_CTX_EFER_LOW_OFFSET 200
#define BOOT_CTX_EFER_HIGH_OFFSET 204
#define SIZE_OF_BOOT_CTX 296
#else
#include <gpr.h>
#define BOOT_CTX_CR0_OFFSET 0U
#define BOOT_CTX_CR3_OFFSET 8U
#define BOOT_CTX_CR4_OFFSET 16U
#define BOOT_CTX_IDT_OFFSET 24U
#define BOOT_CTX_GDT_OFFSET 34U
#define BOOT_CTX_LDT_SEL_OFFSET 44U
#define BOOT_CTX_TR_SEL_OFFSET 46U
#define BOOT_CTX_CS_SEL_OFFSET 48U
#define BOOT_CTX_SS_SEL_OFFSET 50U
#define BOOT_CTX_DS_SEL_OFFSET 52U
#define BOOT_CTX_ES_SEL_OFFSET 54U
#define BOOT_CTX_FS_SEL_OFFSET 56U
#define BOOT_CTX_GS_SEL_OFFSET 58U
#define BOOT_CTX_CS_AR_OFFSET 60U
#define BOOT_CTX_EFER_LOW_OFFSET 64U
#define BOOT_CTX_EFER_HIGH_OFFSET 68U
#define BOOT_CTX_CR0_OFFSET 176U
#define BOOT_CTX_CR3_OFFSET 192U
#define BOOT_CTX_CR4_OFFSET 184U
#define BOOT_CTX_IDT_OFFSET 144U
#define BOOT_CTX_GDT_OFFSET 128U
#define BOOT_CTX_LDT_SEL_OFFSET 280U
#define BOOT_CTX_TR_SEL_OFFSET 282U
#define BOOT_CTX_CS_SEL_OFFSET 268U
#define BOOT_CTX_SS_SEL_OFFSET 270U
#define BOOT_CTX_DS_SEL_OFFSET 272U
#define BOOT_CTX_ES_SEL_OFFSET 274U
#define BOOT_CTX_FS_SEL_OFFSET 276U
#define BOOT_CTX_GS_SEL_OFFSET 278U
#define BOOT_CTX_CS_AR_OFFSET 248U
#define BOOT_CTX_EFER_LOW_OFFSET 200U
#define BOOT_CTX_EFER_HIGH_OFFSET 204U
#define SIZE_OF_BOOT_CTX 296U
struct dt_addr {
/* struct to define how the descriptor stored in memory.
* Refer SDM Vol3 3.5.1 "Segment Descriptor Tables"
* Figure 3-11
*/
struct acrn_descriptor_ptr {
uint16_t limit;
uint64_t base;
uint16_t reserved[3]; /* align struct size to 64bit */
} __attribute__((packed));
struct boot_ctx {
uint64_t cr0;
uint64_t cr3;
uint64_t cr4;
struct dt_addr idt;
struct dt_addr gdt;
uint16_t ldt_sel;
uint16_t tr_sel;
/* align the order to ext_context */
uint16_t cs_sel;
uint16_t ss_sel;
uint16_t ds_sel;
uint16_t es_sel;
uint16_t fs_sel;
uint16_t gs_sel;
uint32_t cs_ar;
uint64_t ia32_efer;
#ifdef CONFIG_EFI_STUB
struct acrn_vcpu_regs {
struct acrn_gp_regs gprs;
uint64_t rip;
uint64_t rflags;
struct acrn_descriptor_ptr gdt;
struct acrn_descriptor_ptr idt;
uint64_t rip;
uint64_t cs_base;
uint64_t cr0;
uint64_t cr4;
uint64_t cr3;
uint64_t ia32_efer;
uint64_t rflags;
uint64_t reserved_64[4];
uint32_t cs_ar;
uint32_t reserved_32[4];
/* don't change the order of following sel */
uint16_t cs_sel;
uint16_t ss_sel;
uint16_t ds_sel;
uint16_t es_sel;
uint16_t fs_sel;
uint16_t gs_sel;
uint16_t ldt_sel;
uint16_t tr_sel;
uint16_t reserved_16[4];
};
struct boot_ctx {
struct acrn_vcpu_regs vcpu_regs;
#ifdef CONFIG_EFI_STUB
void *rsdp;
void *ap_trampoline_buf;
#endif