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hv: add struct acrn_vcpu_regs

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Add struct acrn_vcpu_regs and make struct boot_ctx based on
struct acrn_vcpu_regs.

vm0_boot_context is also changed from struct boot_ctx to struct
acrn_vcpu_regs.

Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
This commit is contained in:
Yin Fengwei 2018-09-28 14:36:53 +08:00 committed by lijinxia
parent 843f7721f0
commit ba1aa40707
5 changed files with 98 additions and 80 deletions
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4
hypervisor/arch/x86/cpu_save_boot_ctx.S
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@ -78,6 +78,6 @@ cpu_primary_save_64:
.align 8 .align 8
.global vm0_boot_context .global vm0_boot_context
vm0_boot_context: vm0_boot_context:
.rept 9 .rept SIZE_OF_BOOT_CTX
.quad 0x0000000000000000 .byte 0x00
.endr .endr

4
hypervisor/arch/x86/guest/vcpu.c
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@ -489,8 +489,8 @@ int prepare_vcpu(struct vm *vm, uint16_t pcpu_id)
vcpu->arch_vcpu.cpu_mode = CPU_MODE_PROTECTED; vcpu->arch_vcpu.cpu_mode = CPU_MODE_PROTECTED;
#else #else
if (is_vm0(vcpu->vm)) { if (is_vm0(vcpu->vm)) {
struct boot_ctx *vm0_init_ctx = struct acrn_vcpu_regs *vm0_init_ctx =
(struct boot_ctx *)(&vm0_boot_context); (struct acrn_vcpu_regs *)(&vm0_boot_context);
/* VM0 bsp start mode is decided by the boot context /* VM0 bsp start mode is decided by the boot context
* setup by bootloader / bios */ * setup by bootloader / bios */
if ((vm0_init_ctx->ia32_efer & MSR_IA32_EFER_LMA_BIT) && if ((vm0_init_ctx->ia32_efer & MSR_IA32_EFER_LMA_BIT) &&

32
hypervisor/arch/x86/static_checks.c
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@ -13,22 +13,22 @@ typedef int CAT_(CTA_DummyType,__LINE__)[(expr) ? 1 : -1]
/* Build time sanity checks to make sure hard-coded offset /* Build time sanity checks to make sure hard-coded offset
* is matching the actual offset! * is matching the actual offset!
*/ */
CTASSERT(BOOT_CTX_CR0_OFFSET == offsetof(struct boot_ctx, cr0)); CTASSERT(BOOT_CTX_CR0_OFFSET == offsetof(struct acrn_vcpu_regs, cr0));
CTASSERT(BOOT_CTX_CR3_OFFSET == offsetof(struct boot_ctx, cr3)); CTASSERT(BOOT_CTX_CR3_OFFSET == offsetof(struct acrn_vcpu_regs, cr3));
CTASSERT(BOOT_CTX_CR4_OFFSET == offsetof(struct boot_ctx, cr4)); CTASSERT(BOOT_CTX_CR4_OFFSET == offsetof(struct acrn_vcpu_regs, cr4));
CTASSERT(BOOT_CTX_IDT_OFFSET == offsetof(struct boot_ctx, idt)); CTASSERT(BOOT_CTX_IDT_OFFSET == offsetof(struct acrn_vcpu_regs, idt));
CTASSERT(BOOT_CTX_GDT_OFFSET == offsetof(struct boot_ctx, gdt)); CTASSERT(BOOT_CTX_GDT_OFFSET == offsetof(struct acrn_vcpu_regs, gdt));
CTASSERT(BOOT_CTX_LDT_SEL_OFFSET == offsetof(struct boot_ctx, ldt_sel)); CTASSERT(BOOT_CTX_LDT_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ldt_sel));
CTASSERT(BOOT_CTX_TR_SEL_OFFSET == offsetof(struct boot_ctx, tr_sel)); CTASSERT(BOOT_CTX_TR_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, tr_sel));
CTASSERT(BOOT_CTX_CS_SEL_OFFSET == offsetof(struct boot_ctx, cs_sel)); CTASSERT(BOOT_CTX_CS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, cs_sel));
CTASSERT(BOOT_CTX_SS_SEL_OFFSET == offsetof(struct boot_ctx, ss_sel)); CTASSERT(BOOT_CTX_SS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ss_sel));
CTASSERT(BOOT_CTX_DS_SEL_OFFSET == offsetof(struct boot_ctx, ds_sel)); CTASSERT(BOOT_CTX_DS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, ds_sel));
CTASSERT(BOOT_CTX_ES_SEL_OFFSET == offsetof(struct boot_ctx, es_sel)); CTASSERT(BOOT_CTX_ES_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, es_sel));
CTASSERT(BOOT_CTX_FS_SEL_OFFSET == offsetof(struct boot_ctx, fs_sel)); CTASSERT(BOOT_CTX_FS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, fs_sel));
CTASSERT(BOOT_CTX_GS_SEL_OFFSET == offsetof(struct boot_ctx, gs_sel)); CTASSERT(BOOT_CTX_GS_SEL_OFFSET == offsetof(struct acrn_vcpu_regs, gs_sel));
CTASSERT(BOOT_CTX_CS_AR_OFFSET == offsetof(struct boot_ctx, cs_ar)); CTASSERT(BOOT_CTX_CS_AR_OFFSET == offsetof(struct acrn_vcpu_regs, cs_ar));
CTASSERT(BOOT_CTX_EFER_LOW_OFFSET == offsetof(struct boot_ctx, ia32_efer)); CTASSERT(BOOT_CTX_EFER_LOW_OFFSET == offsetof(struct acrn_vcpu_regs, ia32_efer));
CTASSERT(BOOT_CTX_EFER_HIGH_OFFSET == offsetof(struct boot_ctx, ia32_efer) + 4); CTASSERT(BOOT_CTX_EFER_HIGH_OFFSET == offsetof(struct acrn_vcpu_regs, ia32_efer) + 4);
CTASSERT(CPU_CONTEXT_OFFSET_RAX == offsetof(struct acrn_gp_regs, rax)); CTASSERT(CPU_CONTEXT_OFFSET_RAX == offsetof(struct acrn_gp_regs, rax));
CTASSERT(CPU_CONTEXT_OFFSET_RBX == offsetof(struct acrn_gp_regs, rbx)); CTASSERT(CPU_CONTEXT_OFFSET_RBX == offsetof(struct acrn_gp_regs, rbx));

10
hypervisor/arch/x86/vmx.c
View File

@ -563,7 +563,8 @@ static void init_guest_context_vm0_bsp(struct vcpu *vcpu)
{ {
struct ext_context *ectx = struct ext_context *ectx =
&vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].ext_ctx; &vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].ext_ctx;
struct boot_ctx * init_ctx = (struct boot_ctx *)(&vm0_boot_context); struct acrn_vcpu_regs* init_ctx =
(struct acrn_vcpu_regs*)(&vm0_boot_context);
uint16_t *sel = &(init_ctx->cs_sel); uint16_t *sel = &(init_ctx->cs_sel);
struct segment_sel *seg; struct segment_sel *seg;
@ -588,9 +589,9 @@ static void init_guest_context_vm0_bsp(struct vcpu *vcpu)
ectx->ldtr.selector = init_ctx->ldt_sel; ectx->ldtr.selector = init_ctx->ldt_sel;
ectx->tr.selector = init_ctx->tr_sel; ectx->tr.selector = init_ctx->tr_sel;
#ifdef CONFIG_EFI_STUB #ifdef CONFIG_EFI_STUB
vcpu_set_rsp(vcpu, efi_ctx->gprs.rsp); vcpu_set_rsp(vcpu, efi_ctx->vcpu_regs.gprs.rsp);
/* clear flags for CF/PF/AF/ZF/SF/OF */ /* clear flags for CF/PF/AF/ZF/SF/OF */
vcpu_set_rflags(vcpu, efi_ctx->rflags & ~(0x8d5UL)); vcpu_set_rflags(vcpu, efi_ctx->vcpu_regs.rflags & ~(0x8d5UL));
#endif #endif
} }
@ -663,7 +664,8 @@ static void init_guest_state(struct vcpu *vcpu)
{ {
struct cpu_context *ctx = struct cpu_context *ctx =
&vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context]; &vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context];
struct boot_ctx * init_ctx = (struct boot_ctx *)(&vm0_boot_context); struct acrn_vcpu_regs* init_ctx =
(struct acrn_vcpu_regs*)(&vm0_boot_context);
enum vm_cpu_mode vcpu_mode = get_vcpu_mode(vcpu); enum vm_cpu_mode vcpu_mode = get_vcpu_mode(vcpu);
vcpu_set_rflags(vcpu, 0x2UL); /* Bit 1 is a active high reserved bit */ vcpu_set_rflags(vcpu, 0x2UL); /* Bit 1 is a active high reserved bit */

128
hypervisor/include/arch/x86/guest/vm0_boot.h
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@ -8,70 +8,86 @@
#define VM0_BOOT_H #define VM0_BOOT_H
#ifdef ASSEMBLER #ifdef ASSEMBLER
#define BOOT_CTX_CR0_OFFSET 0 #define BOOT_CTX_CR0_OFFSET 176
#define BOOT_CTX_CR3_OFFSET 8 #define BOOT_CTX_CR3_OFFSET 192
#define BOOT_CTX_CR4_OFFSET 16 #define BOOT_CTX_CR4_OFFSET 184
#define BOOT_CTX_IDT_OFFSET 24 #define BOOT_CTX_IDT_OFFSET 144
#define BOOT_CTX_GDT_OFFSET 34 #define BOOT_CTX_GDT_OFFSET 128
#define BOOT_CTX_LDT_SEL_OFFSET 44 #define BOOT_CTX_LDT_SEL_OFFSET 280
#define BOOT_CTX_TR_SEL_OFFSET 46 #define BOOT_CTX_TR_SEL_OFFSET 282
#define BOOT_CTX_CS_SEL_OFFSET 48 #define BOOT_CTX_CS_SEL_OFFSET 268
#define BOOT_CTX_SS_SEL_OFFSET 50 #define BOOT_CTX_SS_SEL_OFFSET 270
#define BOOT_CTX_DS_SEL_OFFSET 52 #define BOOT_CTX_DS_SEL_OFFSET 272
#define BOOT_CTX_ES_SEL_OFFSET 54 #define BOOT_CTX_ES_SEL_OFFSET 274
#define BOOT_CTX_FS_SEL_OFFSET 56 #define BOOT_CTX_FS_SEL_OFFSET 276
#define BOOT_CTX_GS_SEL_OFFSET 58 #define BOOT_CTX_GS_SEL_OFFSET 278
#define BOOT_CTX_CS_AR_OFFSET 60 #define BOOT_CTX_CS_AR_OFFSET 248
#define BOOT_CTX_EFER_LOW_OFFSET 64 #define BOOT_CTX_EFER_LOW_OFFSET 200
#define BOOT_CTX_EFER_HIGH_OFFSET 68 #define BOOT_CTX_EFER_HIGH_OFFSET 204
#define SIZE_OF_BOOT_CTX 296
#else #else
#include <gpr.h> #include <gpr.h>
#define BOOT_CTX_CR0_OFFSET 0U #define BOOT_CTX_CR0_OFFSET 176U
#define BOOT_CTX_CR3_OFFSET 8U #define BOOT_CTX_CR3_OFFSET 192U
#define BOOT_CTX_CR4_OFFSET 16U #define BOOT_CTX_CR4_OFFSET 184U
#define BOOT_CTX_IDT_OFFSET 24U #define BOOT_CTX_IDT_OFFSET 144U
#define BOOT_CTX_GDT_OFFSET 34U #define BOOT_CTX_GDT_OFFSET 128U
#define BOOT_CTX_LDT_SEL_OFFSET 44U #define BOOT_CTX_LDT_SEL_OFFSET 280U
#define BOOT_CTX_TR_SEL_OFFSET 46U #define BOOT_CTX_TR_SEL_OFFSET 282U
#define BOOT_CTX_CS_SEL_OFFSET 48U #define BOOT_CTX_CS_SEL_OFFSET 268U
#define BOOT_CTX_SS_SEL_OFFSET 50U #define BOOT_CTX_SS_SEL_OFFSET 270U
#define BOOT_CTX_DS_SEL_OFFSET 52U #define BOOT_CTX_DS_SEL_OFFSET 272U
#define BOOT_CTX_ES_SEL_OFFSET 54U #define BOOT_CTX_ES_SEL_OFFSET 274U
#define BOOT_CTX_FS_SEL_OFFSET 56U #define BOOT_CTX_FS_SEL_OFFSET 276U
#define BOOT_CTX_GS_SEL_OFFSET 58U #define BOOT_CTX_GS_SEL_OFFSET 278U
#define BOOT_CTX_CS_AR_OFFSET 60U #define BOOT_CTX_CS_AR_OFFSET 248U
#define BOOT_CTX_EFER_LOW_OFFSET 64U #define BOOT_CTX_EFER_LOW_OFFSET 200U
#define BOOT_CTX_EFER_HIGH_OFFSET 68U #define BOOT_CTX_EFER_HIGH_OFFSET 204U
#define SIZE_OF_BOOT_CTX 296U
struct dt_addr { /* struct to define how the descriptor stored in memory.
* Refer SDM Vol3 3.5.1 "Segment Descriptor Tables"
* Figure 3-11
*/
struct acrn_descriptor_ptr {
uint16_t limit; uint16_t limit;
uint64_t base; uint64_t base;
uint16_t reserved[3]; /* align struct size to 64bit */
} __attribute__((packed)); } __attribute__((packed));
struct boot_ctx { struct acrn_vcpu_regs {
uint64_t cr0;
uint64_t cr3;
uint64_t cr4;
struct dt_addr idt;
struct dt_addr gdt;
uint16_t ldt_sel;
uint16_t tr_sel;
/* align the order to ext_context */
uint16_t cs_sel;
uint16_t ss_sel;
uint16_t ds_sel;
uint16_t es_sel;
uint16_t fs_sel;
uint16_t gs_sel;
uint32_t cs_ar;
uint64_t ia32_efer;
#ifdef CONFIG_EFI_STUB
struct acrn_gp_regs gprs; struct acrn_gp_regs gprs;
uint64_t rip; struct acrn_descriptor_ptr gdt;
uint64_t rflags; struct acrn_descriptor_ptr idt;
uint64_t rip;
uint64_t cs_base;
uint64_t cr0;
uint64_t cr4;
uint64_t cr3;
uint64_t ia32_efer;
uint64_t rflags;
uint64_t reserved_64[4];
uint32_t cs_ar;
uint32_t reserved_32[4];
/* don't change the order of following sel */
uint16_t cs_sel;
uint16_t ss_sel;
uint16_t ds_sel;
uint16_t es_sel;
uint16_t fs_sel;
uint16_t gs_sel;
uint16_t ldt_sel;
uint16_t tr_sel;
uint16_t reserved_16[4];
};
struct boot_ctx {
struct acrn_vcpu_regs vcpu_regs;
#ifdef CONFIG_EFI_STUB
void *rsdp; void *rsdp;
void *ap_trampoline_buf; void *ap_trampoline_buf;
#endif #endif