dm: initialize vSSRAM buffers

This patch figures out the guest cache hierarchy:
  - calculate the cache hierarchy parameters, including
    cache thread sharing number and inclusiveness of LLC.

  - define and initialize data structure to describe
    L2 & L3 cache buffers, these buffers will be mapped
    to user VM as ssram regions.

  - add some utility functions.

  - complete the implementation of function
    'create_ssram_rtct_entries()', though most functions
    inside are not implemented yet.

Tracked-On: #7010
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Yu1 Wang <yu1.wang@intel.com>

devicemodel/include/types.h

@@ -89,6 +89,12 @@ flsl(uint64_t mask)
 	return mask ? 64 - __builtin_clzl(mask) : 0;
 }
 
+static inline int
+fls(uint32_t mask)
+{
+	return mask ? 32 - __builtin_clz(mask) : 0;
+}
+
 /* Returns the number of 1-bits in bits. */
 static inline int
 bitmap_weight(uint64_t bits)
@@ -129,11 +135,25 @@ static inline uint16_t ffs64(uint64_t value)
 #define mb()    ({ asm volatile("mfence" ::: "memory"); (void)0; })
 
 static inline void
-do_cpuid(u_int ax, u_int *p)
+do_cpuid(uint32_t leaf, uint32_t subleaf, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 {
 	__asm __volatile("cpuid"
-	 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
-	 :  "0" (ax));
+		: "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+		: "a" (leaf), "c" (subleaf)
+		: "memory");
+}
+
+/*
+ * @brief  Get the order value of given count.
+ *
+ * @param  num 32-bits value.
+ *
+ * @return the order value of data on success and -1 on fail.
+ *
+ */
+static inline int get_num_order(uint32_t num)
+{
+	return ((num > 0) ? fls(num - 1) : -1);
 }
 
 #define UGETW(w)            \