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internal commit: 0ab1ea615e5cfbb0687a9d593a86a7b774386076

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Anthony Xu
2018-03-07 21:01:19 +08:00
committed by lijinxia
parent b966397914
commit bd31b1c53e
93 changed files with 37861 additions and 0 deletions
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308
devicemodel/include/public/acrn_common.h Normal file
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/*
* common definition
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright (c) 2017 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* BSD LICENSE
*
* Copyright (C) 2017 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/**
* @file acrn_common.h
*
* @brief acrn common data structure for hypercall or ioctl
*/
#ifndef _ACRN_COMMON_H_
#define _ACRN_COMMON_H_
#include <types.h>
/*
* Common structures for ACRN/VHM/DM
*/
/*
* IO request
*/
#define VHM_REQUEST_MAX 16
#define REQ_STATE_PENDING 0
#define REQ_STATE_SUCCESS 1
#define REQ_STATE_PROCESSING 2
#define REQ_STATE_FAILED -1
#define REQ_PORTIO 0
#define REQ_MMIO 1
#define REQ_PCICFG 2
#define REQ_WP 3
#define REQUEST_READ 0
#define REQUEST_WRITE 1
/**
* @brief Hypercall
*
* @addtogroup acrn_hypercall ACRN Hypercall
* @{
*/
struct mmio_request {
uint32_t direction;
uint32_t reserved;
int64_t address;
int64_t size;
int64_t value;
} __aligned(8);
struct pio_request {
uint32_t direction;
uint32_t reserved;
int64_t address;
int64_t size;
int32_t value;
} __aligned(8);
struct pci_request {
uint32_t direction;
uint32_t reserved[3];/* need keep same header fields with pio_request */
int64_t size;
int32_t value;
int32_t bus;
int32_t dev;
int32_t func;
int32_t reg;
} __aligned(8);
/* vhm_request are 256Bytes aligned */
struct vhm_request {
/* offset: 0bytes - 63bytes */
union {
uint32_t type;
int32_t reserved0[16];
};
/* offset: 64bytes-127bytes */
union {
struct pio_request pio_request;
struct pci_request pci_request;
struct mmio_request mmio_request;
int64_t reserved1[8];
} reqs;
/* True: valid req which need VHM to process.
* ACRN write, VHM read only
**/
int32_t valid;
/* the client which is distributed to handle this request */
int32_t client;
/* 1: VHM had processed and success
* 0: VHM had not yet processed
* -1: VHM failed to process. Invalid request
* VHM write, ACRN read only
*/
int32_t processed;
} __aligned(256);
struct vhm_request_buffer {
union {
struct vhm_request req_queue[VHM_REQUEST_MAX];
int8_t reserved[4096];
};
} __aligned(4096);
/**
* @brief Info to create a VM, the parameter for HC_CREATE_VM hypercall
*/
struct acrn_create_vm {
/** created vmid return to VHM. Keep it first field */
int32_t vmid;
/** vcpu numbers this VM want to create */
uint32_t vcpu_num;
/** the GUID of this VM */
uint8_t GUID[16];
/** whether Secure World is enabled for this VM */
uint8_t secure_world_enabled;
/** Reserved for future use*/
uint8_t reserved[31];
} __aligned(8);
/**
* @brief Info to create a vcpu
*
* the parameter for HC_CREATE_VCPU hypercall
*/
struct acrn_create_vcpu {
/** the virtual cpu id for the vcpu want to create */
uint32_t vcpu_id;
/** the physical cpu id for the vcpu want to create */
uint32_t pcpu_id;
} __aligned(8);
/**
* @brief Info to set ioreq buffer for a created VM
*
* the parameter for HC_SET_IOREQ_BUFFER hypercall
*/
struct acrn_set_ioreq_buffer {
/** gpa of per VM request_buffer */
uint64_t req_buf;
} __aligned(8);
/** Interrupt type for acrn_irqline: inject interrupt to IOAPIC */
#define ACRN_INTR_TYPE_ISA 0
/** Interrupt type for acrn_irqline: inject interrupt to both PIC and IOAPIC */
#define ACRN_INTR_TYPE_IOAPIC 1
/**
* @brief Info to assert/deassert/pulse a virtual irq line for a VM
*
* the parameter for HC_ASSERT_IRQLINE/HC_DEASSERT_IRQLINE/HC_PULSE_IRQLINE
* hypercall
*/
struct acrn_irqline {
/** interrupt type which could be IOAPIC or ISA */
uint32_t intr_type;
/** reserved for alignment padding */
uint32_t reserved;
/** pic irq for ISA type */
uint64_t pic_irq;
/** ioapic irq for IOAPIC & ISA TYPE,
* if -1 then this irq will not be injected
*/
uint64_t ioapic_irq;
} __aligned(8);
/**
* @brief Info to inject a msi interrupt for a VM
*
* the parameter for HC_INJECT_MSI hypercall
*/
struct acrn_msi_entry {
/** msi addr[19:12] with dest vcpu id */
uint64_t msi_addr;
/** msi data[7:0] with vector */
uint64_t msi_data;
} __aligned(8);
/**
* @brief Info to inject a nmi interrupt for a VM
*/
struct acrn_nmi_entry {
/** virtual cpu id to inject */
int64_t vcpu_id;
} __aligned(8);
/**
* @brief Info to remap pass-through pci msi for a VM
*
* the parameter for HC_VM_PCI_MSIX_REMAP hypercall
*/
struct acrn_vm_pci_msix_remap {
/** pass-through pci device virtual BDF# */
uint16_t virt_bdf;
/** pass-through pci device physical BDF# */
uint16_t phys_bdf;
/** pass-through pci device MSI/x cap control data */
uint16_t msi_ctl;
/** reserved for alignment padding */
uint16_t reserved;
/** pass-through pci device msi address to remap, which will
* return the caller after remapping
*/
uint64_t msi_addr; /* IN/OUT: msi address to fix */
/** pass-through pci device msi data to remap, which will
* return the caller after remapping
*/
uint32_t msi_data;
/** pass-through pci device is msi or msix
* 0 - MSI, 1 - MSI-X
*/
int32_t msix;
/** if the pass-through pci device is msix, this field contains
* the MSI-X entry table index
*/
int32_t msix_entry_index;
/** if the pass-through pci device is msix, this field contains
* Vector Control for MSI-X Entry, field defined in MSIX spec
*/
uint32_t vector_ctl;
} __aligned(8);
/**
* @brief The guest config pointer offset.
*
* It's designed to support passing DM config data pointer, based on it,
* hypervisor would parse then pass DM defined configration to GUEST vcpu
* when booting guest VM.
* the address 0xd0000 here is designed by DM, as it arranged all memory
* layout below 1M, DM should make sure there is no overlap for the address
* 0xd0000 usage.
*/
#define GUEST_CFG_OFFSET 0xd0000
/**
* @}
*/
#endif /* _ACRN_COMMON_H_ */

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devicemodel/include/public/vhm_ioctl_defs.h Normal file
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/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* Copyright (c) 2017 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* BSD LICENSE
*
* Copyright (C) 2017 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/**
* @file vhm_ioctl_defs.h
*
* @brief Virtio and Hypervisor Module definition for ioctl to user space
*/
#ifndef _VHM_IOCTL_DEFS_H_
#define _VHM_IOCTL_DEFS_H_
/* Commmon structures for ACRN/VHM/DM */
#include "acrn_common.h"
/*
* Commmon IOCTL ID defination for VHM/DM
*/
#define _IC_ID(x, y) (((x)<<24)|(y))
#define IC_ID 0x43UL
/* General */
#define IC_ID_GEN_BASE 0x0UL
#define IC_GET_API_VERSION _IC_ID(IC_ID, IC_ID_GEN_BASE + 0x00)
/* VM management */
#define IC_ID_VM_BASE 0x10UL
#define IC_CREATE_VM _IC_ID(IC_ID, IC_ID_VM_BASE + 0x00)
#define IC_DESTROY_VM _IC_ID(IC_ID, IC_ID_VM_BASE + 0x01)
#define IC_START_VM _IC_ID(IC_ID, IC_ID_VM_BASE + 0x02)
#define IC_PAUSE_VM _IC_ID(IC_ID, IC_ID_VM_BASE + 0x03)
#define IC_CREATE_VCPU _IC_ID(IC_ID, IC_ID_VM_BASE + 0x04)
/* IRQ and Interrupts */
#define IC_ID_IRQ_BASE 0x20UL
#define IC_ASSERT_IRQLINE _IC_ID(IC_ID, IC_ID_IRQ_BASE + 0x00)
#define IC_DEASSERT_IRQLINE _IC_ID(IC_ID, IC_ID_IRQ_BASE + 0x01)
#define IC_PULSE_IRQLINE _IC_ID(IC_ID, IC_ID_IRQ_BASE + 0x02)
#define IC_INJECT_MSI _IC_ID(IC_ID, IC_ID_IRQ_BASE + 0x03)
/* DM ioreq management */
#define IC_ID_IOREQ_BASE 0x30UL
#define IC_SET_IOREQ_BUFFER _IC_ID(IC_ID, IC_ID_IOREQ_BASE + 0x00)
#define IC_NOTIFY_REQUEST_FINISH _IC_ID(IC_ID, IC_ID_IOREQ_BASE + 0x01)
#define IC_CREATE_IOREQ_CLIENT _IC_ID(IC_ID, IC_ID_IOREQ_BASE + 0x02)
#define IC_ATTACH_IOREQ_CLIENT _IC_ID(IC_ID, IC_ID_IOREQ_BASE + 0x03)
#define IC_DESTROY_IOREQ_CLIENT _IC_ID(IC_ID, IC_ID_IOREQ_BASE + 0x04)
/* Guest memory management */
#define IC_ID_MEM_BASE 0x40UL
#define IC_ALLOC_MEMSEG _IC_ID(IC_ID, IC_ID_MEM_BASE + 0x00)
#define IC_SET_MEMSEG _IC_ID(IC_ID, IC_ID_MEM_BASE + 0x01)
/* PCI assignment*/
#define IC_ID_PCI_BASE 0x50UL
#define IC_ASSIGN_PTDEV _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x00)
#define IC_DEASSIGN_PTDEV _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x01)
#define IC_VM_PCI_MSIX_REMAP _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x02)
#define IC_SET_PTDEV_INTR_INFO _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x03)
#define IC_RESET_PTDEV_INTR_INFO _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x04)
/**
* struct vm_memseg - memory segment info for guest
*
* @len: length of memory segment
* @gpa: guest physical start address of memory segment
*/
struct vm_memseg {
uint64_t len;
uint64_t gpa;
};
#define VM_SYSMEM 0
#define VM_MMIO 1
/**
* struct vm_memmap - EPT memory mapping info for guest
*
* @type: memory mapping type
* @gpa: guest physical start address of memory mapping
* @hpa: host physical start address of memory
* @len: the length of memory range mapped
* @prot: memory mapping attribute
*/
struct vm_memmap {
uint32_t type;
uint32_t reserved;
uint64_t gpa;
uint64_t hpa; /* only for type == VM_MMIO */
uint64_t len; /* mmap length */
uint32_t prot; /* RWX */
};
/**
* struct ic_ptdev_irq - pass thru device irq data structure
*/
struct ic_ptdev_irq {
#define IRQ_INTX 0
#define IRQ_MSI 1
#define IRQ_MSIX 2
/** @type: irq type */
uint32_t type;
/** @virt_bdf: virtual bdf description of pass thru device */
uint16_t virt_bdf; /* IN: Device virtual BDF# */
/** @phy_bdf: physical bdf description of pass thru device */
uint16_t phys_bdf; /* IN: Device physical BDF# */
/** union */
union {
/** struct intx - info of IOAPIC/PIC interrupt */
struct {
/** @virt_pin: virtual IOAPIC pin */
uint32_t virt_pin;
/** @phys_pin: physical IOAPIC pin */
uint32_t phys_pin;
/** @pic_pin: PIC pin */
uint32_t is_pic_pin;
} intx;
/** struct msix - info of MSI/MSIX interrupt */
struct {
/* Keep this filed on top of msix */
/** @vector_cnt: vector count of MSI/MSIX */
uint32_t vector_cnt;
/** @table_size: size of MSIX table(round up to 4K) */
uint32_t table_size;
/** @table_paddr: physical address of MSIX table */
uint64_t table_paddr;
} msix;
};
};
/**
* struct ioreq_notify - data strcture to notify hypervisor ioreq is handled
*
* @client_id: client id to identify ioreq client
* @vcpu: identify the ioreq submitter
*/
struct ioreq_notify {
int32_t client_id;
uint32_t vcpu;
};
/**
* struct api_version - data structure to track VHM API version
*
* @major_version: major version of VHM API
* @minor_version: minor version of VHM API
*/
struct api_version {
uint32_t major_version;
uint32_t minor_version;
};
#endif /* VHM_IOCTL_DEFS_H */