mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-26 07:21:37 +00:00
Patch for modularising ioapic.[c/h] and related files.
This adds few functions to access the daata structures defined inside ioapic.c. Removes the same data structures from ioapic.h Also this modifies some of the names of existing APIs to conform to the ioapic module name. Modified gsi_table identifier to gs_table_data, to avoid a MISRA C Violation. Tracked-On: #1842 Signed-off-by: Arindam Roy <arindam.roy@intel.com>
This commit is contained in:
Arindam Roy
wenlingz
parent
af9b747629
commit
bec21d147b
@ -5,6 +5,7 @@
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*/
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#include <hypervisor.h>
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#include <ioapic.h>
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/*
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* lookup a ptdev entry by sid
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@ -286,11 +287,11 @@ static struct ptirq_remapping_info *add_intx_remapping(struct acrn_vm *vm, uint8
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uint8_t vpin_src = pic_pin ? PTDEV_VPIN_PIC : PTDEV_VPIN_IOAPIC;
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DEFINE_IOAPIC_SID(phys_sid, phys_pin, 0);
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DEFINE_IOAPIC_SID(virt_sid, virt_pin, vpin_src);
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uint32_t phys_irq = pin_to_irq(phys_pin);
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uint32_t phys_irq = ioapic_pin_to_irq(phys_pin);
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if ((!pic_pin && (virt_pin >= vioapic_pincount(vm))) || (pic_pin && (virt_pin >= vpic_pincount()))) {
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pr_err("ptirq_add_intx_remapping fails!\n");
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} else if (!irq_is_gsi(phys_irq)) {
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} else if (!ioapic_irq_is_gsi(phys_irq)) {
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pr_err("%s, invalid phys_pin: %d <-> irq: 0x%x is not a GSI\n", __func__, phys_pin, phys_irq);
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} else {
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entry = ptirq_lookup_entry_by_sid(PTDEV_INTR_INTX, &phys_sid, NULL);
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@ -352,7 +353,7 @@ static void remove_intx_remapping(struct acrn_vm *vm, uint8_t virt_pin, bool pic
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if (is_entry_active(entry)) {
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phys_irq = entry->allocated_pirq;
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/* disable interrupt */
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gsi_mask_irq(phys_irq);
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ioapic_gsi_mask_irq(phys_irq);
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ptirq_deactivate_entry(entry);
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dev_dbg(ACRN_DBG_IRQ,
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@ -510,7 +511,7 @@ void ptirq_intx_ack(struct acrn_vm *vm, uint8_t virt_pin,
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dev_dbg(ACRN_DBG_PTIRQ, "dev-assign: irq=0x%x acked vr: 0x%x",
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phys_irq, irq_to_vector(phys_irq));
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gsi_unmask_irq(phys_irq);
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ioapic_gsi_unmask_irq(phys_irq);
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}
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}
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@ -580,7 +581,7 @@ static void activate_physical_ioapic(struct acrn_vm *vm,
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bool is_lvl_trigger = false;
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/* disable interrupt */
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gsi_mask_irq(phys_irq);
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ioapic_gsi_mask_irq(phys_irq);
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/* build physical IOAPIC RTE */
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rte = ptirq_build_physical_rte(vm, entry);
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@ -597,7 +598,7 @@ static void activate_physical_ioapic(struct acrn_vm *vm,
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ioapic_set_rte(phys_irq, rte);
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if (intr_mask == IOAPIC_RTE_INTMCLR) {
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gsi_unmask_irq(phys_irq);
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ioapic_gsi_unmask_irq(phys_irq);
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}
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}
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@ -647,7 +648,7 @@ int32_t ptirq_intx_pin_remap(struct acrn_vm *vm, uint8_t virt_pin, uint8_t vpin_
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* switch vpin source is needed
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*/
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if (virt_pin < NR_LEGACY_PIN) {
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uint8_t vpin = pic_ioapic_pin_map[virt_pin];
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uint8_t vpin = get_pic_pin_from_ioapic_pin(virt_pin);
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entry = ptirq_lookup_entry_by_vpin(vm, vpin, !pic_pin);
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if (entry != NULL) {
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@ -661,7 +662,7 @@ int32_t ptirq_intx_pin_remap(struct acrn_vm *vm, uint8_t virt_pin, uint8_t vpin_
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/* fix vPIC pin to correct native IOAPIC pin */
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if (pic_pin) {
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phys_pin = pic_ioapic_pin_map[virt_pin];
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phys_pin = get_pic_pin_from_ioapic_pin(virt_pin);
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}
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entry = add_intx_remapping(vm,
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virt_pin, phys_pin, pic_pin);
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@ -5,12 +5,20 @@
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*/
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#include <hypervisor.h>
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#include <ioapic.h>
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#define IOAPIC_MAX_PIN 240U
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#define IOAPIC_INVALID_PIN 0xffU
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struct gsi_table gsi_table[NR_MAX_GSI];
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uint32_t nr_gsi;
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/*
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* IOAPIC_MAX_LINES is architecturally defined.
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* The usable RTEs may be a subset of the total on a per IO APIC basis.
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*/
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#define IOAPIC_MAX_LINES 120U
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#define NR_MAX_GSI (NR_IOAPICS * IOAPIC_MAX_LINES)
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static struct gsi_table gsi_table_data[NR_MAX_GSI];
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static uint32_t ioapic_nr_gsi;
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static spinlock_t ioapic_lock;
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static union ioapic_rte saved_rte[NR_IOAPICS][IOAPIC_MAX_PIN];
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@ -76,6 +84,26 @@ const uint8_t pic_ioapic_pin_map[NR_LEGACY_PIN] = {
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15U, /* pin15*/
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};
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uint8_t get_pic_pin_from_ioapic_pin (uint8_t pin_index) {
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uint8_t pin_id = IOAPIC_INVALID_PIN;
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if (pin_index < NR_LEGACY_PIN) {
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pin_id = pic_ioapic_pin_map[pin_index];
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}
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return pin_id;
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}
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void *ioapic_get_gsi_irq_addr (uint32_t irq_num) {
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void *addr = NULL;
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if (irq_num < NR_MAX_GSI) {
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addr = gsi_table_data[irq_num].addr;
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}
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return addr;
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}
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uint32_t ioapic_get_nr_gsi (void) {
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return ioapic_nr_gsi;
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}
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static void *map_ioapic(uint64_t ioapic_paddr)
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{
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/* At some point we may need to translate this paddr to a vaddr.
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@ -199,9 +227,9 @@ static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
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void *addr;
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union ioapic_rte rte;
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addr = gsi_table[gsi].addr;
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addr = gsi_table_data[gsi].addr;
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rte = create_rte_for_gsi_irq(gsi, vr);
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ioapic_set_rte_entry(addr, gsi_table[gsi].pin, rte);
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ioapic_set_rte_entry(addr, gsi_table_data[gsi].pin, rte);
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if ((rte.full & IOAPIC_RTE_TRGRMOD) != 0UL) {
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set_irq_trigger_mode(gsi, true);
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@ -210,7 +238,7 @@ static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
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}
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dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
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gsi, gsi_table[gsi].pin,
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gsi, gsi_table_data[gsi].pin,
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rte.full);
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}
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@ -221,9 +249,9 @@ void ioapic_get_rte(uint32_t irq, union ioapic_rte *rte)
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{
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void *addr;
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if (irq_is_gsi(irq)) {
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addr = gsi_table[irq].addr;
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ioapic_get_rte_entry(addr, gsi_table[irq].pin, rte);
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if (ioapic_irq_is_gsi(irq)) {
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addr = gsi_table_data[irq].addr;
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ioapic_get_rte_entry(addr, gsi_table_data[irq].pin, rte);
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}
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}
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@ -231,27 +259,27 @@ void ioapic_set_rte(uint32_t irq, union ioapic_rte rte)
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{
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void *addr;
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if (irq_is_gsi(irq)) {
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addr = gsi_table[irq].addr;
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ioapic_set_rte_entry(addr, gsi_table[irq].pin, rte);
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if (ioapic_irq_is_gsi(irq)) {
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addr = gsi_table_data[irq].addr;
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ioapic_set_rte_entry(addr, gsi_table_data[irq].pin, rte);
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dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
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irq, gsi_table[irq].pin,
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irq, gsi_table_data[irq].pin,
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rte.full);
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}
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}
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bool irq_is_gsi(uint32_t irq)
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bool ioapic_irq_is_gsi(uint32_t irq)
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{
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return irq < nr_gsi;
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return irq < ioapic_nr_gsi;
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}
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uint8_t irq_to_pin(uint32_t irq)
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uint8_t ioapic_irq_to_pin(uint32_t irq)
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{
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uint8_t ret;
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if (irq_is_gsi(irq)) {
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ret = gsi_table[irq].pin;
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if (ioapic_irq_is_gsi(irq)) {
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ret = gsi_table_data[irq].pin;
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} else {
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ret = IOAPIC_INVALID_PIN;
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}
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@ -259,13 +287,17 @@ uint8_t irq_to_pin(uint32_t irq)
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return ret;
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}
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uint32_t pin_to_irq(uint8_t pin)
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bool ioapic_is_pin_valid (uint8_t pin) {
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return (pin != IOAPIC_INVALID_PIN);
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}
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uint32_t ioapic_pin_to_irq(uint8_t pin)
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{
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uint32_t i;
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uint32_t irq = IRQ_INVALID;
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for (i = 0U; i < nr_gsi; i++) {
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if (gsi_table[i].pin == pin) {
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for (i = 0U; i < ioapic_nr_gsi; i++) {
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if (gsi_table_data[i].pin == pin) {
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irq = i;
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break;
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}
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@ -274,36 +306,40 @@ uint32_t pin_to_irq(uint8_t pin)
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}
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static void
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irq_gsi_mask_unmask(uint32_t irq, bool mask)
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ioapic_irq_gsi_mask_unmask(uint32_t irq, bool mask)
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{
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void *addr;
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void *addr = NULL;
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uint8_t pin;
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union ioapic_rte rte;
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if (irq_is_gsi(irq)) {
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addr = gsi_table[irq].addr;
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pin = gsi_table[irq].pin;
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if (ioapic_irq_is_gsi(irq)) {
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addr = gsi_table_data[irq].addr;
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pin = gsi_table_data[irq].pin;
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ioapic_get_rte_entry(addr, pin, &rte);
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if (mask) {
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rte.full |= IOAPIC_RTE_INTMSET;
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if (addr != NULL) {
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ioapic_get_rte_entry(addr, pin, &rte);
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if (mask) {
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rte.full |= IOAPIC_RTE_INTMSET;
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} else {
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rte.full &= ~IOAPIC_RTE_INTMASK;
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}
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ioapic_set_rte_entry(addr, pin, rte);
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dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
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irq, pin, rte.full);
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} else {
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rte.full &= ~IOAPIC_RTE_INTMASK;
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dev_dbg(ACRN_DBG_PTIRQ, "NULL Address returned from gsi_table_data");
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}
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ioapic_set_rte_entry(addr, pin, rte);
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dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
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irq, pin, rte.full);
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}
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}
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void gsi_mask_irq(uint32_t irq)
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void ioapic_gsi_mask_irq(uint32_t irq)
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{
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irq_gsi_mask_unmask(irq, true);
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ioapic_irq_gsi_mask_unmask(irq, true);
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}
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void gsi_unmask_irq(uint32_t irq)
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void ioapic_gsi_unmask_irq(uint32_t irq)
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{
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irq_gsi_mask_unmask(irq, false);
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ioapic_irq_gsi_mask_unmask(irq, false);
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}
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static uint8_t
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@ -327,7 +363,7 @@ ioapic_nr_pins(void *ioapic_base)
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return nr_pins;
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}
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void setup_ioapic_irqs(void)
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void ioapic_setup_irqs(void)
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{
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uint8_t ioapic_id;
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uint32_t gsi = 0U;
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@ -345,14 +381,14 @@ void setup_ioapic_irqs(void)
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nr_pins = ioapic_nr_pins(addr);
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for (pin = 0U; pin < nr_pins; pin++) {
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gsi_table[gsi].ioapic_id = ioapic_id;
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gsi_table[gsi].addr = addr;
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gsi_table_data[gsi].ioapic_id = ioapic_id;
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gsi_table_data[gsi].addr = addr;
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if (gsi < NR_LEGACY_IRQ) {
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gsi_table[gsi].pin =
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gsi_table_data[gsi].pin =
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legacy_irq_to_pin[gsi] & 0xffU;
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} else {
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gsi_table[gsi].pin = pin;
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gsi_table_data[gsi].pin = pin;
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}
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/* pinned irq before use it */
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@ -382,8 +418,8 @@ void setup_ioapic_irqs(void)
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}
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/* system max gsi numbers */
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nr_gsi = gsi;
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ASSERT(nr_gsi <= NR_MAX_GSI, "GSI table overflow");
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ioapic_nr_gsi = gsi;
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ASSERT(ioapic_nr_gsi <= NR_MAX_GSI, "GSI table overflow");
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}
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void suspend_ioapic(void)
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@ -6,6 +6,7 @@
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#include <hypervisor.h>
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#include <softirq.h>
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#include <ioapic.h>
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static spinlock_t exception_spinlock = { .head = 0U, .tail = 0U, };
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static spinlock_t irq_alloc_spinlock = { .head = 0U, .tail = 0U, };
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@ -69,7 +70,7 @@ static void free_irq_num(uint32_t irq)
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uint64_t rflags;
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if (irq < NR_IRQS) {
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if (!irq_is_gsi(irq)) {
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if (!ioapic_irq_is_gsi(irq)) {
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spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
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(void)bitmap_test_and_clear_nolock((uint16_t)(irq & 0x3FU),
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irq_alloc_bitmap + (irq >> 6U));
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@ -288,7 +289,7 @@ static inline bool irq_need_mask(const struct irq_desc *desc)
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{
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/* level triggered gsi should be masked */
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return (((desc->flags & IRQF_LEVEL) != 0U)
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&& irq_is_gsi(desc->irq));
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&& ioapic_irq_is_gsi(desc->irq));
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}
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static inline bool irq_need_unmask(const struct irq_desc *desc)
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@ -296,7 +297,7 @@ static inline bool irq_need_unmask(const struct irq_desc *desc)
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/* level triggered gsi for non-ptdev should be unmasked */
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return (((desc->flags & IRQF_LEVEL) != 0U)
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&& ((desc->flags & IRQF_PT) == 0U)
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&& irq_is_gsi(desc->irq));
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&& ioapic_irq_is_gsi(desc->irq));
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}
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static inline void handle_irq(const struct irq_desc *desc)
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@ -304,7 +305,7 @@ static inline void handle_irq(const struct irq_desc *desc)
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irq_action_t action = desc->action;
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if (irq_need_mask(desc)) {
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gsi_mask_irq(desc->irq);
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ioapic_gsi_mask_irq(desc->irq);
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}
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/* Send EOI to LAPIC/IOAPIC IRR */
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@ -315,7 +316,7 @@ static inline void handle_irq(const struct irq_desc *desc)
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}
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if (irq_need_unmask(desc)) {
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gsi_unmask_irq(desc->irq);
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ioapic_gsi_unmask_irq(desc->irq);
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}
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}
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@ -429,7 +430,7 @@ void init_default_irqs(uint16_t cpu_id)
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/* we use ioapic only, disable legacy PIC */
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disable_pic_irqs();
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setup_ioapic_irqs();
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ioapic_setup_irqs();
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init_softirq();
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}
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}
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@ -4,6 +4,7 @@
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*/
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#include <hypervisor.h>
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#include <trampoline.h>
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#include <ioapic.h>
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struct cpu_context cpu_ctx;
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@ -5,6 +5,7 @@
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*/
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#include <hypervisor.h>
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#include <ioapic.h>
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#include "shell_priv.h"
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#define TEMP_STR_SIZE 60U
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@ -1120,6 +1121,7 @@ static int32_t get_ioapic_info(char *str_arg, size_t str_max_len)
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char *str = str_arg;
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uint32_t irq;
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size_t len, size = str_max_len;
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uint32_t ioapic_nr_gsi = 0U;
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len = snprintf(str, size, "\r\nIRQ\tPIN\tRTE.HI32\tRTE.LO32\tVEC\tDST\tDM\tTM\tDELM\tIRR\tMASK");
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if (len >= size) {
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@ -1128,14 +1130,20 @@ static int32_t get_ioapic_info(char *str_arg, size_t str_max_len)
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size -= len;
|
||||
str += len;
|
||||
|
||||
for (irq = 0U; irq < nr_gsi; irq++) {
|
||||
void *addr = gsi_table[irq].addr;
|
||||
uint8_t pin = gsi_table[irq].pin;
|
||||
ioapic_nr_gsi = ioapic_get_nr_gsi ();
|
||||
for (irq = 0U; irq < ioapic_nr_gsi; irq++) {
|
||||
void *addr = ioapic_get_gsi_irq_addr (irq);
|
||||
uint8_t pin = ioapic_irq_to_pin (irq);
|
||||
union ioapic_rte rte;
|
||||
|
||||
bool irr, phys, level, mask;
|
||||
uint32_t delmode, vector, dest;
|
||||
|
||||
/* Add NULL check for addr, INVALID_PIN check for pin */
|
||||
if ((addr == NULL) || (!ioapic_is_pin_valid(pin))) {
|
||||
goto overflow;
|
||||
}
|
||||
|
||||
ioapic_get_rte_entry(addr, pin, &rte);
|
||||
|
||||
get_rte_info(rte, &mask, &irr, &phys, &delmode, &level, &vector, &dest);
|
||||
|
||||
@ -29,6 +29,7 @@
|
||||
*/
|
||||
|
||||
#include <hypervisor.h>
|
||||
#include <ioapic.h>
|
||||
|
||||
#include "uart16550.h"
|
||||
|
||||
|
||||
@ -11,7 +11,6 @@
|
||||
#include <gdt.h>
|
||||
#include <idt.h>
|
||||
#include <apicreg.h>
|
||||
#include <ioapic.h>
|
||||
#include <lapic.h>
|
||||
#include <msr.h>
|
||||
#include <io.h>
|
||||
|
||||
@ -9,26 +9,19 @@
|
||||
|
||||
#include <bsp_extern.h>
|
||||
|
||||
/*
|
||||
* IOAPIC_MAX_LINES is architecturally defined.
|
||||
* The usable RTEs may be a subset of the total on a per IO APIC basis.
|
||||
*/
|
||||
#define IOAPIC_MAX_LINES 120U
|
||||
#define NR_LEGACY_IRQ 16U
|
||||
#define NR_LEGACY_PIN NR_LEGACY_IRQ
|
||||
#define NR_MAX_GSI (NR_IOAPICS * IOAPIC_MAX_LINES)
|
||||
void ioapic_setup_irqs(void);
|
||||
|
||||
void setup_ioapic_irqs(void);
|
||||
|
||||
bool irq_is_gsi(uint32_t irq);
|
||||
uint8_t irq_to_pin(uint32_t irq);
|
||||
bool ioapic_irq_is_gsi(uint32_t irq);
|
||||
uint8_t ioapic_irq_to_pin(uint32_t irq);
|
||||
|
||||
/**
|
||||
* @brief Get irq num from pin num
|
||||
*
|
||||
* @param[in] pin The pin number
|
||||
*/
|
||||
uint32_t pin_to_irq(uint8_t pin);
|
||||
uint32_t ioapic_pin_to_irq(uint8_t pin);
|
||||
|
||||
/**
|
||||
* @brief Set the redirection table entry
|
||||
@ -55,8 +48,8 @@ void ioapic_get_rte(uint32_t irq, union ioapic_rte *rte);
|
||||
void suspend_ioapic(void);
|
||||
void resume_ioapic(void);
|
||||
|
||||
void gsi_mask_irq(uint32_t irq);
|
||||
void gsi_unmask_irq(uint32_t irq);
|
||||
void ioapic_gsi_mask_irq(uint32_t irq);
|
||||
void ioapic_gsi_unmask_irq(uint32_t irq);
|
||||
|
||||
void ioapic_get_rte_entry(void *ioapic_addr, uint8_t pin, union ioapic_rte *rte);
|
||||
|
||||
@ -66,8 +59,9 @@ struct gsi_table {
|
||||
void *addr;
|
||||
};
|
||||
|
||||
extern struct gsi_table gsi_table[NR_MAX_GSI];
|
||||
extern uint32_t nr_gsi;
|
||||
extern const uint8_t pic_ioapic_pin_map[NR_LEGACY_PIN];
|
||||
void *ioapic_get_gsi_irq_addr(uint32_t irq_num);
|
||||
uint32_t ioapic_get_nr_gsi(void);
|
||||
uint8_t get_pic_pin_from_ioapic_pin(uint8_t pin_index);
|
||||
bool ioapic_is_pin_valid(uint8_t pin);
|
||||
|
||||
#endif /* IOAPIC_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user