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hv: vpci: reshuffle pci_bar structure
The current code declare pci_bar structure following the PCI bar spec. However, we could not tell whether the value in virtual BAR configuration space is valid base address base on current pci_bar structure. We need to add more fields which are duplicated instances of the vBAR information. Basides these fields which will added, bar_base_mapped is another duplicated instance of the vBAR information. This patch try to reshuffle the pci_bar structure to declare pci_bar structure following the software implement benefit not the PCI bar spec. Tracked-On: #3475 Signed-off-by: Li Fei1 <fei1.li@intel.com>
This commit is contained in:
Li Fei1
wenlingz
parent
f53baadd5a
commit
c049c5c965
@ -32,68 +32,6 @@
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#include <logmsg.h>
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#include "vpci_priv.h"
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/**
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* @brief get bar's full base address in 64-bit
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* @pre (pci_get_bar_type(bars[idx].reg.value) == PCIBAR_MEM64) ? ((idx + 1U) < nr_bars) : (idx < nr_bars)
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* For 64-bit MMIO bar, its lower 32-bits base address and upper 32-bits base are combined
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* into one 64-bit base address
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*/
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static uint64_t pci_bar_2_bar_base(const struct pci_bar *bars, uint32_t nr_bars, uint32_t idx)
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{
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uint64_t base = 0UL;
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uint64_t tmp;
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const struct pci_bar *bar;
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enum pci_bar_type type;
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bar = &bars[idx];
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type = pci_get_bar_type(bar->reg.value);
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switch (type) {
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case PCIBAR_IO_SPACE:
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/* IO bar, BITS 31-2 = base address, 4-byte aligned */
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base = (uint64_t)(bar->reg.bits.io.base);
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base <<= 2U;
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break;
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case PCIBAR_MEM32:
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base = (uint64_t)(bar->reg.bits.mem.base);
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base <<= 4U;
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break;
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case PCIBAR_MEM64:
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if ((idx + 1U) < nr_bars) {
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const struct pci_bar *next_bar = &bars[idx + 1U];
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/* Upper 32-bit of 64-bit bar */
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base = (uint64_t)(next_bar->reg.value);
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base <<= 32U;
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/* Lower 32-bit of a 64-bit bar (BITS 31-4 = base address, 16-byte aligned) */
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tmp = (uint64_t)(bar->reg.bits.mem.base);
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tmp <<= 4U;
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base |= tmp;
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}
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break;
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default:
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/* Nothing to do */
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break;
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}
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return base;
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}
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/**
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* @brief get vbar's full base address in 64-bit
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* For 64-bit MMIO bar, its lower 32-bits base address and upper 32-bits base are combined
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* into one 64-bit base address
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* @pre vdev != NULL
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*/
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static uint64_t get_vbar_base(const struct pci_vdev *vdev, uint32_t idx)
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{
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return pci_bar_2_bar_base(&vdev->bar[0], vdev->nr_bars, idx);
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}
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/**
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* @pre vdev != NULL
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*/
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@ -120,11 +58,11 @@ static void vdev_pt_unmap_mem_vbar(struct pci_vdev *vdev, uint32_t idx)
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vbar = &vdev->bar[idx];
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if (vdev->bar_base_mapped[idx] != 0UL) {
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if (vbar->base != 0UL) {
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ept_del_mr(vm, (uint64_t *)(vm->arch_vm.nworld_eptp),
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vdev->bar_base_mapped[idx], /* GPA (old vbar) */
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vbar->base, /* GPA (old vbar) */
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vbar->size);
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vdev->bar_base_mapped[idx] = 0UL;
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vbar->base = 0UL;
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}
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is_msix_table_bar = (has_msix_cap(vdev) && (idx == vdev->msix.table_bar));
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@ -169,7 +107,7 @@ static void vdev_pt_map_mem_vbar(struct pci_vdev *vdev, uint32_t idx)
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vbar = &vdev->bar[idx];
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vbar_base = get_vbar_base(vdev, idx);
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vbar_base = pci_vdev_get_bar_base(vdev, idx);
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if (vbar_base != 0UL) {
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if (ept_is_mr_valid(vm, vbar_base, vbar->size)) {
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uint64_t hpa = gpa2hpa(vdev->vpci->vm, vbar_base);
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@ -183,7 +121,7 @@ static void vdev_pt_map_mem_vbar(struct pci_vdev *vdev, uint32_t idx)
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EPT_WR | EPT_RD | EPT_UNCACHED);
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}
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/* Remember the previously mapped MMIO vbar */
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vdev->bar_base_mapped[idx] = vbar_base;
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vbar->base = vbar_base;
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} else {
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pr_fatal("%s, %x:%x.%x set invalid bar[%d] address: 0x%lx\n", __func__,
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vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx, vbar_base);
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@ -195,8 +133,8 @@ static void vdev_pt_map_mem_vbar(struct pci_vdev *vdev, uint32_t idx)
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uint64_t addr_hi, addr_lo;
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struct pci_msix *msix = &vdev->msix;
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if (vdev->bar_base_mapped[idx] != 0UL) {
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addr_lo = vdev->bar_base_mapped[idx] + msix->table_offset;
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if (vbar->base != 0UL) {
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addr_lo = vbar->base + msix->table_offset;
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addr_hi = addr_lo + (msix->table_count * MSIX_TABLE_ENTRY_SIZE);
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addr_lo = round_page_down(addr_lo);
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@ -204,7 +142,7 @@ static void vdev_pt_map_mem_vbar(struct pci_vdev *vdev, uint32_t idx)
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register_mmio_emulation_handler(vm, vmsix_table_mmio_access_handler,
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addr_lo, addr_hi, vdev);
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ept_del_mr(vm, (uint64_t *)vm->arch_vm.nworld_eptp, addr_lo, addr_hi - addr_lo);
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msix->mmio_gpa = vdev->bar_base_mapped[idx];
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msix->mmio_gpa = vbar->base;
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}
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}
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}
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@ -220,11 +158,11 @@ static void vdev_pt_allow_io_vbar(struct pci_vdev *vdev, uint32_t idx)
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/* For SOS, all port IO access is allowed by default, so skip SOS here */
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if (!is_sos_vm(vdev->vpci->vm)) {
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struct pci_bar *vbar = &vdev->bar[idx];
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uint64_t vbar_base = get_vbar_base(vdev, idx); /* vbar (gpa) */
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uint64_t vbar_base = pci_vdev_get_bar_base(vdev, idx); /* vbar (gpa) */
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if (vbar_base != 0UL) {
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allow_guest_pio_access(vdev->vpci->vm, (uint16_t)vbar_base, (uint32_t)(vbar->size));
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/* Remember the previously allowed IO vbar base */
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vdev->bar_base_mapped[idx] = vbar_base;
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vbar->base = vbar_base;
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}
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}
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}
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@ -240,117 +178,56 @@ static void vdev_pt_deny_io_vbar(struct pci_vdev *vdev, uint32_t idx)
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/* For SOS, all port IO access is allowed by default, so skip SOS here */
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if (!is_sos_vm(vdev->vpci->vm)) {
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struct pci_bar *vbar = &vdev->bar[idx];
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if (vdev->bar_base_mapped[idx] != 0UL) {
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deny_guest_pio_access(vdev->vpci->vm, (uint16_t)(vdev->bar_base_mapped[idx]),
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(uint32_t)(vbar->size));
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vdev->bar_base_mapped[idx] = 0UL;
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if (vbar->base != 0UL) {
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deny_guest_pio_access(vdev->vpci->vm, (uint16_t)(vbar->base), (uint32_t)(vbar->size));
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vbar->base = 0UL;
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}
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}
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}
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/**
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* @brief Set the base address portion of the vbar base address register (32-bit)
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* base: bar value with flags portion masked off
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* @pre vbar != NULL
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*/
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static void set_vbar_base(struct pci_bar *vbar, uint32_t base)
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{
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union pci_bar_reg bar_reg;
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bar_reg.value = base;
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if (vbar->is_64bit_high) {
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/* Upper 32-bit of a 64-bit bar does not have the flags portion */
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vbar->reg.value = bar_reg.value;
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} else if (vbar->reg.bits.io.is_io == 1U) {
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/* IO bar, BITS 31-2 = base address, 4-byte aligned */
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vbar->reg.bits.io.base = bar_reg.bits.io.base;
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} else {
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/* MMIO bar, BITS 31-4 = base address, 16-byte aligned */
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vbar->reg.bits.mem.base = bar_reg.bits.mem.base;
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}
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}
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/**
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* @pre vdev != NULL
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*/
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static void vdev_pt_write_vbar(struct pci_vdev *vdev, uint32_t offset, uint32_t val)
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void vdev_pt_write_vbar(struct pci_vdev *vdev, uint32_t idx, uint32_t val)
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{
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uint32_t idx;
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uint64_t base;
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bool bar_update_normal;
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struct pci_bar *vbar;
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bool update_bar = false;
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uint32_t update_idx = idx;
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uint32_t offset = pci_bar_offset(idx);
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struct pci_bar *vbar = &vdev->bar[idx];
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base = 0UL;
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idx = (offset - pci_bar_offset(0U)) >> 2U;
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bar_update_normal = (val != (uint32_t)~0U);
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switch (vbar->type) {
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case PCIBAR_IO_SPACE:
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vdev_pt_deny_io_vbar(vdev, update_idx);
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if (val != ~0U) {
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pci_vdev_write_bar(vdev, idx, val);
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vdev_pt_allow_io_vbar(vdev, update_idx);
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} else {
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pci_vdev_write_cfg_u32(vdev, offset, vbar->mask);
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}
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break;
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vbar = &vdev->bar[idx];
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if (vbar->is_64bit_high) {
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if (idx > 0U) {
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uint32_t prev_idx = idx - 1U;
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vdev_pt_unmap_mem_vbar(vdev, prev_idx);
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base = git_size_masked_bar_base(vdev->bar[prev_idx].size, ((uint64_t)val) << 32U) >> 32U;
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set_vbar_base(vbar, (uint32_t)base);
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if (bar_update_normal) {
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vdev_pt_map_mem_vbar(vdev, prev_idx);
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case PCIBAR_MEM64HI:
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update_idx = idx - 1U;
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/* falls through */
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case PCIBAR_MEM32:
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update_bar = true;
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/* falls through */
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case PCIBAR_MEM64:
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vdev_pt_unmap_mem_vbar(vdev, update_idx);
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if (val != ~0U) {
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pci_vdev_write_bar(vdev, idx, val);
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if (update_bar) {
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vdev_pt_map_mem_vbar(vdev, update_idx);
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}
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} else {
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ASSERT(false, "idx for upper 32-bit of the 64-bit bar should be greater than 0!");
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pci_vdev_write_cfg_u32(vdev, offset, vbar->mask);
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}
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} else {
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enum pci_bar_type type = pci_get_bar_type(vbar->reg.value);
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break;
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switch (type) {
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case PCIBAR_IO_SPACE:
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vdev_pt_deny_io_vbar(vdev, idx);
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base = git_size_masked_bar_base(vbar->size, (uint64_t)val) & 0xffffUL;
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set_vbar_base(vbar, (uint32_t)base);
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if (bar_update_normal) {
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vdev_pt_allow_io_vbar(vdev, idx);
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}
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break;
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case PCIBAR_MEM32:
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vdev_pt_unmap_mem_vbar(vdev, idx);
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base = git_size_masked_bar_base(vbar->size, (uint64_t)val);
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set_vbar_base(vbar, (uint32_t)base);
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if (bar_update_normal) {
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vdev_pt_map_mem_vbar(vdev, idx);
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}
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break;
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case PCIBAR_MEM64:
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vdev_pt_unmap_mem_vbar(vdev, idx);
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base = git_size_masked_bar_base(vbar->size, (uint64_t)val);
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set_vbar_base(vbar, (uint32_t)base);
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break;
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default:
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/* Nothing to do */
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break;
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}
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}
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/* Write the vbar value to corresponding virtualized vbar reg */
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pci_vdev_write_cfg_u32(vdev, offset, vbar->reg.value);
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}
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/**
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* @pre vdev != NULL
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* bar write access must be 4 bytes and offset must also be 4 bytes aligned, it will be dropped otherwise
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*/
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void vdev_pt_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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/* bar write access must be 4 bytes and offset must also be 4 bytes aligned */
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if ((bytes == 4U) && ((offset & 0x3U) == 0U)) {
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vdev_pt_write_vbar(vdev, offset, val);
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default:
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/* Nothing to do */
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break;
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}
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}
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@ -414,8 +291,10 @@ void init_vdev_pt(struct pci_vdev *vdev)
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size32 = pci_pdev_read_cfg(pbdf, offset, 4U);
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pci_pdev_write_cfg(pbdf, offset, 4U, lo);
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vbar->type = type;
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vbar->mask = size32 & mask;
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vbar->fixed = lo & (~mask);
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vbar->size = (uint64_t)size32 & mask;
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vbar->reg.value = lo;
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if (is_prelaunched_vm(vdev->vpci->vm)) {
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lo = (uint32_t)vdev->pci_dev_config->vbar_base[idx];
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@ -433,20 +312,20 @@ void init_vdev_pt(struct pci_vdev *vdev)
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vbar->size = round_page_up(vbar->size);
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vbar = &vdev->bar[idx];
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vbar->is_64bit_high = true;
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vbar->reg.value = hi;
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vbar->mask = size32;
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vbar->type = PCIBAR_MEM64HI;
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if (is_prelaunched_vm(vdev->vpci->vm)) {
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hi = (uint32_t)(vdev->pci_dev_config->vbar_base[idx - 1U] >> 32U);
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}
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vdev_pt_write_vbar(vdev, pci_bar_offset(idx - 1U), lo);
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vdev_pt_write_vbar(vdev, pci_bar_offset(idx), hi);
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vdev_pt_write_vbar(vdev, idx - 1U, lo);
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vdev_pt_write_vbar(vdev, idx, hi);
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} else {
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vbar->size = vbar->size & ~(vbar->size - 1UL);
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if (type == PCIBAR_MEM32) {
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vbar->size = round_page_up(vbar->size);
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}
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vdev_pt_write_vbar(vdev, pci_bar_offset(idx), lo);
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vdev_pt_write_vbar(vdev, idx, lo);
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}
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}
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}
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@ -91,3 +91,47 @@ struct pci_vdev *pci_find_vdev(struct acrn_vpci *vpci, union pci_bdf vbdf)
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return vdev;
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}
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void pci_vdev_write_bar(struct pci_vdev *vdev, uint32_t idx, uint32_t val)
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{
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struct pci_bar *vbar;
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uint32_t bar, offset;
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vbar = &vdev->bar[idx];
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bar = val & vbar->mask;
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bar |= vbar->fixed;
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offset = pci_bar_offset(idx);
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pci_vdev_write_cfg_u32(vdev, offset, bar);
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}
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uint64_t pci_vdev_get_bar_base(const struct pci_vdev *vdev, uint32_t idx)
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{
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const struct pci_bar *vbar;
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enum pci_bar_type type;
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uint64_t base = 0UL;
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uint32_t lo, hi, offset;
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vbar = &vdev->bar[idx];
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offset = pci_bar_offset(idx);
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lo = pci_vdev_read_cfg_u32(vdev, offset);
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if ((vbar->type != PCIBAR_NONE) && (lo != ~0U)) {
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type = vbar->type;
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base = lo & vbar->mask;
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if (vbar->type == PCIBAR_MEM64) {
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vbar = &vdev->bar[idx + 1U];
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hi = pci_vdev_read_cfg_u32(vdev, offset + 4U);
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if (hi != ~0U) {
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hi &= vbar->mask;
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base |= ((uint64_t)hi << 32U);
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} else {
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base = 0UL;
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}
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}
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if (type == PCIBAR_IO_SPACE) {
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base &= 0xffffUL;
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}
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}
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return base;
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}
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@ -329,7 +329,10 @@ static int32_t vpci_write_pt_dev_cfg(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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if (vbar_access(vdev, offset)) {
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vdev_pt_write_cfg(vdev, offset, bytes, val);
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/* bar write access must be 4 bytes and offset must also be 4 bytes aligned */
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if ((bytes == 4U) && ((offset & 0x3U) == 0U)) {
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vdev_pt_write_vbar(vdev, pci_bar_index(offset), val);
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}
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} else if (msicap_access(vdev, offset)) {
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vmsi_write_cfg(vdev, offset, bytes, val);
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} else if (msixcap_access(vdev, offset)) {
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@ -127,7 +127,7 @@ static inline bool msicap_access(const struct pci_vdev *vdev, uint32_t offset)
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void init_vdev_pt(struct pci_vdev *vdev);
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void vdev_pt_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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void vdev_pt_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
|
||||
void vdev_pt_write_vbar(struct pci_vdev *vdev, uint32_t idx, uint32_t val);
|
||||
|
||||
void init_vmsi(struct pci_vdev *vdev);
|
||||
void vmsi_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
|
||||
@ -145,4 +145,6 @@ void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes,
|
||||
|
||||
struct pci_vdev *pci_find_vdev(struct acrn_vpci *vpci, union pci_bdf vbdf);
|
||||
|
||||
void pci_vdev_write_bar(struct pci_vdev *vdev, uint32_t idx, uint32_t val);
|
||||
uint64_t pci_vdev_get_bar_base(const struct pci_vdev *vdev, uint32_t idx);
|
||||
#endif /* VPCI_PRIV_H_ */
|
||||
|
||||
@ -34,6 +34,15 @@
|
||||
#include <pci.h>
|
||||
|
||||
|
||||
struct pci_bar {
|
||||
enum pci_bar_type type;
|
||||
uint64_t size; /* BAR size */
|
||||
uint64_t base; /* BAR guest physical address */
|
||||
uint64_t base_hpa; /* BAR host physical address */
|
||||
uint32_t fixed; /* BAR fix memory type encoding */
|
||||
uint32_t mask; /* BAR size mask */
|
||||
};
|
||||
|
||||
struct msix_table_entry {
|
||||
uint64_t addr;
|
||||
uint32_t data;
|
||||
@ -61,8 +70,8 @@ struct pci_msix {
|
||||
|
||||
union pci_cfgdata {
|
||||
uint8_t data_8[PCI_REGMAX + 1U];
|
||||
uint16_t data_16[(PCI_REGMAX + 1U) >> 2U];
|
||||
uint32_t data_32[(PCI_REGMAX + 1U) >> 4U];
|
||||
uint16_t data_16[(PCI_REGMAX + 1U) >> 1U];
|
||||
uint32_t data_32[(PCI_REGMAX + 1U) >> 2U];
|
||||
};
|
||||
|
||||
struct pci_vdev;
|
||||
@ -86,9 +95,6 @@ struct pci_vdev {
|
||||
uint32_t nr_bars; /* 6 for normal device, 2 for bridge, 1 for cardbus */
|
||||
struct pci_bar bar[PCI_BAR_COUNT];
|
||||
|
||||
/* Remember the previously mapped/registered vbar base for undo purpose */
|
||||
uint64_t bar_base_mapped[PCI_BAR_COUNT];
|
||||
|
||||
struct pci_msi msi;
|
||||
struct pci_msix msix;
|
||||
|
||||
|
||||
@ -151,47 +151,7 @@ enum pci_bar_type {
|
||||
PCIBAR_IO_SPACE,
|
||||
PCIBAR_MEM32,
|
||||
PCIBAR_MEM64,
|
||||
};
|
||||
|
||||
/*
|
||||
* Base Address Register for MMIO, pf=prefetchable, type=0 (32-bit), 1 (<=1MB), 2 (64-bit):
|
||||
* 31 4 3 2 1 0
|
||||
* +----------+--------------+-------------+
|
||||
* | Base address |pf| type | 0 |
|
||||
* +---------------------------------------+
|
||||
*
|
||||
* Base Address Register for IO (R=reserved):
|
||||
* 31 2 1 0
|
||||
* +----------+----------------------------+
|
||||
* | Base address | R | 1 |
|
||||
* +---------------------------------------+
|
||||
*/
|
||||
union pci_bar_reg {
|
||||
uint32_t value;
|
||||
|
||||
/* Base address + flags portion */
|
||||
union {
|
||||
struct {
|
||||
uint32_t is_io:1; /* 0 for memory */
|
||||
uint32_t type:2;
|
||||
uint32_t prefetchable:1;
|
||||
uint32_t base:28; /* BITS 31-4 = base address, 16-byte aligned */
|
||||
} mem;
|
||||
|
||||
struct {
|
||||
uint32_t is_io:1; /* 1 for I/O */
|
||||
uint32_t:1;
|
||||
uint32_t base:30; /* BITS 31-2 = base address, 4-byte aligned */
|
||||
} io;
|
||||
} bits;
|
||||
};
|
||||
|
||||
struct pci_bar {
|
||||
/* Base Address Register */
|
||||
union pci_bar_reg reg;
|
||||
uint64_t size;
|
||||
uint64_t base_hpa;
|
||||
bool is_64bit_high; /* true if this is the upper 32-bit of a 64-bit bar */
|
||||
PCIBAR_MEM64HI,
|
||||
};
|
||||
|
||||
/* Basic MSIX capability info */
|
||||
@ -221,6 +181,11 @@ static inline uint32_t pci_bar_offset(uint32_t idx)
|
||||
return PCIR_BARS + (idx << 2U);
|
||||
}
|
||||
|
||||
static inline uint32_t pci_bar_index(uint32_t offset)
|
||||
{
|
||||
return (offset - PCIR_BARS) >> 2U;
|
||||
}
|
||||
|
||||
static inline bool is_bar_offset(uint32_t nr_bars, uint32_t offset)
|
||||
{
|
||||
bool ret;
|
||||
@ -244,7 +209,6 @@ static inline enum pci_bar_type pci_get_bar_type(uint32_t val)
|
||||
} else {
|
||||
switch (val & PCIM_BAR_MEM_TYPE) {
|
||||
case PCIM_BAR_MEM_32:
|
||||
case PCIM_BAR_MEM_1MB:
|
||||
type = PCIBAR_MEM32;
|
||||
break;
|
||||
|
||||
@ -261,19 +225,6 @@ static inline enum pci_bar_type pci_get_bar_type(uint32_t val)
|
||||
return type;
|
||||
}
|
||||
|
||||
/**
|
||||
* Given bar size and raw bar value, return bar base address by masking off its lower flag bits
|
||||
* size/val: all in 64-bit values to accommodate 64-bit MMIO bar size masking
|
||||
*/
|
||||
static inline uint64_t git_size_masked_bar_base(uint64_t size, uint64_t val)
|
||||
{
|
||||
uint64_t mask;
|
||||
|
||||
mask = ~(size - 1UL);
|
||||
|
||||
return (mask & val);
|
||||
}
|
||||
|
||||
static inline bool bdf_is_equal(union pci_bdf a, union pci_bdf b)
|
||||
{
|
||||
return (a.value == b.value);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user