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https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-19 04:02:05 +00:00
hv: vmsix: refine vmsix remap
Do vMSI-X remap only when Mask Bit in Vector Control Register for MSI-X Table Entry is unmask. The previous implementation also has two issues: 1. It only check whether Message Control Register for MSI-X has been modified when guest writes MSI-X CFG space at Message Control Register offset. 2. It doesn't really disable MSI-X when guest wants to disable MSI-X. Tracked-On: #3475 Signed-off-by: Li Fei1 <fei1.li@intel.com>
This commit is contained in:
Li Fei1
wenlingz
parent
5f5ba1d647
commit
c05d9f8086
@ -46,27 +46,52 @@ static inline bool msixtable_access(const struct pci_vdev *vdev, uint32_t offset
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return in_range(offset, vdev->msix.table_offset, vdev->msix.table_count * MSIX_TABLE_ENTRY_SIZE);
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}
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/**
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* @pre vdev != NULL
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*/
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static inline struct msix_table_entry *get_msix_table_entry(const struct pci_vdev *vdev, uint32_t index)
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{
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void *hva = hpa2hva(vdev->msix.mmio_hpa + vdev->msix.table_offset);
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return ((struct msix_table_entry *)hva + index);
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}
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/**
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* @pre vdev != NULL
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*/
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static void mask_one_msix_vector(const struct pci_vdev *vdev, uint32_t index)
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{
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uint32_t vector_control;
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struct msix_table_entry *pentry = get_msix_table_entry(vdev, index);
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stac();
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vector_control = pentry->vector_control | PCIM_MSIX_VCTRL_MASK;
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mmio_write32(vector_control, (void *)&(pentry->vector_control));
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clac();
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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* @pre vdev->vpci->vm != NULL
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* @pre vdev->pdev != NULL
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*/
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static int32_t remap_vmsix_entry(const struct pci_vdev *vdev, uint32_t index, bool enable)
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static void remap_one_vmsix_entry(const struct pci_vdev *vdev, uint32_t index)
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{
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const struct msix_table_entry *ventry;
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struct msix_table_entry *pentry;
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struct ptirq_msi_info info;
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void *hva;
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struct ptirq_msi_info info = {};
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int32_t ret;
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mask_one_msix_vector(vdev, index);
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ventry = &vdev->msix.table_entries[index];
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if ((ventry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0U) {
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info.vmsi_addr.full = vdev->msix.table_entries[index].addr;
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info.vmsi_data.full = (enable) ? vdev->msix.table_entries[index].data : 0U;
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info.vmsi_data.full = vdev->msix.table_entries[index].data;
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ret = ptirq_prepare_msix_remap(vdev->vpci->vm, vdev->bdf.value, vdev->pdev->bdf.value, (uint16_t)index, &info);
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if (ret == 0) {
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/* Write the table entry to the physical structure */
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hva = hpa2hva(vdev->msix.mmio_hpa + vdev->msix.table_offset);
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pentry = (struct msix_table_entry *)hva + index;
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pentry = get_msix_table_entry(vdev, index);
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/*
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* PCI 3.0 Spec allows writing to Message Address and Message Upper Address
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@ -81,86 +106,8 @@ static int32_t remap_vmsix_entry(const struct pci_vdev *vdev, uint32_t index, bo
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mmio_write32(vdev->msix.table_entries[index].vector_control, (void *)&(pentry->vector_control));
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clac();
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}
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return ret;
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->pdev != NULL
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*/
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static inline void enable_disable_msix(const struct pci_vdev *vdev, bool enable)
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{
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uint32_t msgctrl;
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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if (enable) {
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msgctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
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} else {
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msgctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
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}
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pci_pdev_write_cfg(vdev->pdev->bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U, msgctrl);
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}
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/**
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* Do MSI-X remap for all MSI-X table entries in the target device
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* @pre vdev != NULL
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* @pre vdev->pdev != NULL
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*/
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static int32_t remap_vmsix(const struct pci_vdev *vdev, bool enable)
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{
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uint32_t index;
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int32_t ret = 0;
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/* disable MSI-X during configuration */
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enable_disable_msix(vdev, false);
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for (index = 0U; index < vdev->msix.table_count; index++) {
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ret = remap_vmsix_entry(vdev, index, enable);
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if (ret != 0) {
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break;
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}
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}
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if (ret == 0) {
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if (enable) {
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enable_disable_pci_intx(vdev->pdev->bdf, false);
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}
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enable_disable_msix(vdev, enable);
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}
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return ret;
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}
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/**
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* Do MSI-X remap for one MSI-X table entry only
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* @pre vdev != NULL
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* @pre vdev->pdev != NULL
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*/
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static int32_t remap_one_vmsx_entry(const struct pci_vdev *vdev, uint32_t index, bool enable)
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{
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uint32_t msgctrl;
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int32_t ret;
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/* disable MSI-X during configuration */
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enable_disable_msix(vdev, false);
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ret = remap_vmsix_entry(vdev, index, enable);
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if (ret == 0) {
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if (enable) {
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enable_disable_pci_intx(vdev->pdev->bdf, false);
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}
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/* Restore MSI-X Enable bit */
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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if ((msgctrl & PCIM_MSIXCTRL_MSIX_ENABLE) == PCIM_MSIXCTRL_MSIX_ENABLE) {
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pci_pdev_write_cfg(vdev->pdev->bdf, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U, msgctrl);
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}
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}
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return ret;
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}
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/**
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@ -180,26 +127,19 @@ void vmsix_read_cfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes
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*/
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void vmsix_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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uint32_t msgctrl;
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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uint32_t old_msgctrl, msgctrl;
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old_msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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/* Write to vdev */
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pci_vdev_write_cfg(vdev, offset, bytes, val);
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msgctrl = pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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/* Writing Message Control field? */
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if ((offset - vdev->msix.capoff) == PCIR_MSIX_CTRL) {
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if (((msgctrl ^ val) & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) {
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if ((val & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) {
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(void)remap_vmsix(vdev, true);
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} else {
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(void)remap_vmsix(vdev, false);
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}
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}
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if (((msgctrl ^ val) & PCIM_MSIXCTRL_FUNCTION_MASK) != 0U) {
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pci_pdev_write_cfg(vdev->pdev->bdf, offset, 2U, val);
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if (((old_msgctrl ^ msgctrl) & (PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK)) != 0U) {
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if ((msgctrl & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) {
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enable_disable_pci_intx(vdev->pdev->bdf, false);
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}
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pci_pdev_write_cfg(vdev->pdev->bdf, offset, 2U, msgctrl);
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}
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}
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@ -207,12 +147,10 @@ void vmsix_write_cfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uin
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* @pre vdev != NULL
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* @pre mmio != NULL
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*/
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static void rw_vmsix_table(const struct pci_vdev *vdev, struct mmio_request *mmio, uint32_t offset)
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static void rw_vmsix_table(struct pci_vdev *vdev, struct mmio_request *mmio, uint32_t offset)
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{
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const struct msix_table_entry *entry;
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uint32_t vector_control, entry_offset, table_offset, index;
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bool message_changed = false;
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bool unmasked;
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struct msix_table_entry *entry;
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uint32_t entry_offset, table_offset, index;
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/* Find out which entry it's accessing */
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table_offset = offset - vdev->msix.table_offset;
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@ -228,43 +166,10 @@ static void rw_vmsix_table(const struct pci_vdev *vdev, struct mmio_request *mmi
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} else {
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/* Only DWORD and QWORD are permitted */
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if ((mmio->size == 4U) || (mmio->size == 8U)) {
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/* Save for comparison */
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vector_control = entry->vector_control;
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/*
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* Writing different value to Message Data/Addr?
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* PCI Spec: Software is permitted to fill in MSI-X Table entry DWORD fields
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* individually with DWORD writes, or software in certain cases is permitted
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* to fill in appropriate pairs of DWORDs with a single QWORD write
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*/
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if (entry_offset < offsetof(struct msix_table_entry, data)) {
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uint64_t qword_mask = ~0UL;
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if (mmio->size == 4U) {
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qword_mask = (entry_offset == 0U) ?
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0x00000000FFFFFFFFUL : 0xFFFFFFFF00000000UL;
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}
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message_changed = ((entry->addr & qword_mask) != (mmio->value & qword_mask));
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} else {
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if (entry_offset == offsetof(struct msix_table_entry, data)) {
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message_changed = (entry->data != (uint32_t)mmio->value);
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}
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}
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/* Write to pci_vdev */
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(void)memcpy_s((void *)entry + entry_offset, (size_t)mmio->size,
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&mmio->value, (size_t)mmio->size);
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/* If MSI-X hasn't been enabled, do nothing */
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if ((pci_vdev_read_cfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U)
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& PCIM_MSIXCTRL_MSIX_ENABLE) == PCIM_MSIXCTRL_MSIX_ENABLE) {
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if ((((entry->vector_control ^ vector_control) & PCIM_MSIX_VCTRL_MASK) != 0U)
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|| message_changed) {
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unmasked = ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0U);
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(void)remap_one_vmsx_entry(vdev, index, unmasked);
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}
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}
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remap_one_vmsix_entry(vdev, index);
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} else {
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pr_err("%s, Only DWORD and QWORD are permitted", __func__);
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}
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