diff --git a/devicemodel/core/sw_load_common.c b/devicemodel/core/sw_load_common.c
index a94176438..199f98d21 100644
--- a/devicemodel/core/sw_load_common.c
+++ b/devicemodel/core/sw_load_common.c
@@ -56,10 +56,11 @@ static char bootargs[BOOT_ARG_LEN];
  * 2:       0x100000 -  lowmem      RAM             lowmem - 1MB
  * 3:         lowmem -  0x80000000  (reserved)      2GB - lowmem
  * 4:	  0x80000000 -  0x88000000  (reserved)	    128MB
- * 5:     0xDF000000 -  0xE0000000  (reserved)      16MB
- * 6:     0xE0000000 -  0x100000000 MCFG, MMIO      512MB
- * 7:    0x100000000 -  0x140000000 64-bit PCI hole 1GB
- * 8:    0x140000000 -  highmem     RAM             highmem - 5GB
+ * 5:     0xDB000000 -  0xDF000000  (reserved)      64MB
+ * 6:     0xDF000000 -  0xE0000000  (reserved)      16MB
+ * 7:     0xE0000000 -  0x100000000 MCFG, MMIO      512MB
+ * 8:    0x100000000 -  0x140000000 64-bit PCI hole 1GB
+ * 9:    0x140000000 -  highmem     RAM             highmem - 5GB
  */
 const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
 	{	/* 0 to video memory */
@@ -93,6 +94,19 @@ const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
 		.type     = E820_TYPE_RESERVED
 	},
 
+	{
+		/* reserve for GVT-d graphics stolen memory.
+		 * The native BIOS allocates the stolen memory by itself,
+		 * and size can be configured by user itself through BIOS GUI.
+		 * For ACRN, we simply hard code to 64MB and static
+		 * reserved the memory region to avoid more efforts in OVMF,
+		 * and user *must* align the native BIOS setting to 64MB.
+		 */
+		.baseaddr = 0xDB000000,
+		.length	  = 0x4000000,
+		.type     = E820_TYPE_RESERVED
+	},
+
 	{
 		/* reserve for GVT */
 		.baseaddr = 0xDF000000,
diff --git a/devicemodel/include/sw_load.h b/devicemodel/include/sw_load.h
index 746681d79..ef71e3647 100644
--- a/devicemodel/include/sw_load.h
+++ b/devicemodel/include/sw_load.h
@@ -39,9 +39,9 @@
 #define E820_TYPE_ACPI_NVS      4U   /* EFI 10 */
 #define E820_TYPE_UNUSABLE      5U   /* EFI 8 */
 
-#define NUM_E820_ENTRIES        9
+#define NUM_E820_ENTRIES        10
 #define LOWRAM_E820_ENTRY       2
-#define HIGHRAM_E820_ENTRY      8
+#define HIGHRAM_E820_ENTRY      9
 
 /* Defines a single entry in an E820 memory map. */
 struct e820_entry {