hv: Inter-VM communication config for hybrid_rt on whl-ipc-i5

add an IVSHMEM regoin and the related configuration parameters in
hybrid_rt scenario on whl-ipc-i5. The size of the shared memory is
2M, and it is used for the communication between VM0 and VM2.

v6: rename shm name; remove unnecessary MACROs.

v7: rename MACRO for shm name; add unassigned vbdf for post-launched
    VMs.

Tracked-On: #4853

Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

hypervisor/include/arch/x86/vm_config.h

@@ -140,10 +140,14 @@ struct acrn_vm_os_config {
 	uint64_t kernel_ramdisk_addr;
 } __aligned(8);
 
+/* the vbdf is assgined by device model */
+#define UNASSIGNED_VBDF        0xFFFFU
+
 struct acrn_vm_pci_dev_config {
 	uint32_t emu_type;				/* the type how the device is emulated. */
 	union pci_bdf vbdf;				/* virtual BDF of PCI device */
 	union pci_bdf pbdf;				/* physical BDF of PCI device */
+	char shm_region_name[32];			/* TODO: combine pbdf and shm_region_name into a union member */
 	uint64_t vbar_base[PCI_BAR_COUNT];		/* vbar base address of PCI device */
 	struct pci_pdev *pdev;				/* the physical PCI device if it's a PT device */
 	const struct pci_vdev_ops *vdev_ops;		/* operations for PCI CFG read/write */

misc/hv_prebuild/vm_cfg_checks.c

@@ -9,6 +9,7 @@
 #include <vm_config.h>
 #include <rdt.h>
 #include <vuart.h>
+#include <ivshmem.h>
 #include <vpci.h>
 #include <hv_prebuild.h>
 
@@ -21,6 +22,7 @@ static uint8_t safety_vm_uuid1[16] = SAFETY_VM_UUID1;
 /* sanity check for below structs is not needed, so use a empty struct instead */
 struct acrn_vm_pci_dev_config sos_pci_devs[CONFIG_MAX_PCI_DEV_NUM];
 const struct pci_vdev_ops vhostbridge_ops;
+const struct pci_vdev_ops vpci_ivshmem_ops;
 
 #define PLATFORM_CPUS_MASK             ((1UL << MAX_PCPU_NUM) - 1UL)
 

misc/vm_configs/boards/whl-ipc-i5/pci_devices.h

@@ -58,4 +58,6 @@
 
 #define ETHERNET_CONTROLLER_1                   .pbdf.bits = {.b = 0x04U, .d = 0x00U, .f = 0x00U}
 
+#define IVSHMEM_SHM_REGION_0                    "hv:/shm_region_0"
+
 #endif /* PCI_DEVICES_H_ */

misc/vm_configs/scenarios/hybrid_rt/vm_configurations.c

@@ -8,6 +8,7 @@
 #include <pci_dev.h>
 
 extern struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM];
+extern struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM];
 
 struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 	{	/* VM0 */
@@ -84,6 +85,9 @@ struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
 	},
 	{	/* VM2 */
 		CONFIG_POST_STD_VM(1),
+		/* The PCI device configuration is only for in-hypervisor vPCI devices. */
+		.pci_dev_num = VM2_CONFIG_PCI_DEV_NUM,
+		.pci_devs = vm2_pci_devs,
 		.cpu_affinity = VM2_CONFIG_CPU_AFFINITY,
 		.vuart[0] = {
 			.type = VUART_LEGACY_PIO,

misc/vm_configs/scenarios/hybrid_rt/vm_configurations.h

@@ -27,7 +27,7 @@
 #define VM0_CONFIG_MEM_SIZE             0x40000000UL
 #define VM0_CONFIG_MEM_START_HPA2       0x0UL
 #define VM0_CONFIG_MEM_SIZE_HPA2        0x0UL
-#define VM0_CONFIG_PCI_DEV_NUM          3U
+#define VM0_CONFIG_PCI_DEV_NUM          4U
 
 /* SOS_VM == VM1 */
 #define SOS_VM_BOOTARGS			SOS_ROOTFS	\
@@ -38,5 +38,6 @@
 #define SOS_VM_CONFIG_CPU_AFFINITY      (AFFINITY_CPU(0U) | AFFINITY_CPU(1U))
 
 #define VM2_CONFIG_CPU_AFFINITY         (AFFINITY_CPU(1U))
+#define VM2_CONFIG_PCI_DEV_NUM          1U
 
 #endif /* VM_CONFIGURATIONS_H */

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/ivshmem_cfg.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2020 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef IVSHMEM_CFG_H
+#define IVSHMEM_CFG_H
+
+#include <ivshmem.h>
+#include <pgtable.h>
+#include <pci_devices.h>
+
+/*
+ * The IVSHMEM_SHM_SIZE is the sum of all memory regions.
+ * The size range of each memory region is [2M, 1G) and is a power of 2.
+ */
+#define IVSHMEM_SHM_SIZE	0x200000UL
+#define IVSHMEM_DEV_NUM		2UL
+
+/* All user defined memory regions */
+
+struct ivshmem_shm_region mem_regions[] = {
+	{
+		.name = IVSHMEM_SHM_REGION_0,
+		.size = 0x200000UL,		/* 2M */
+	},
+};
+
+#endif /* IVSHMEM_CFG_H */

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/pci_dev.c

@@ -10,9 +10,18 @@
 #include <vbar_base.h>
 #include <mmu.h>
 #include <page.h>
+#include <ivshmem.h>
 
+/*
+ * TODO: remove PTDEV macro and add DEV_PRIVINFO macro to initialize pbdf for
+ * passthrough device configuration and shm_name for ivshmem device configuration.
+ */
 #define PTDEV(PCI_DEV)		PCI_DEV, PCI_DEV##_VBAR
 
+/*
+ * TODO: add DEV_PCICOMMON macro to initialize emu_type, vbdf and vdev_ops
+ * to simplify the code.
+ */
 struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
 	{
 		.emu_type = PCI_DEV_TYPE_HVEMUL,
@@ -29,4 +38,20 @@ struct acrn_vm_pci_dev_config vm0_pci_devs[VM0_CONFIG_PCI_DEV_NUM] = {
 		.vbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U},
 		PTDEV(ETHERNET_CONTROLLER_0),
 	},
+	{
+		.emu_type = PCI_DEV_TYPE_HVEMUL,
+		.vbdf.bits = {.b = 0x00U, .d = 0x03U, .f = 0x00U},
+		.vdev_ops = &vpci_ivshmem_ops,
+		.shm_region_name = IVSHMEM_SHM_REGION_0,
+		IVSHMEM_DEVICE_0_VBAR
+	},
+};
+
+struct acrn_vm_pci_dev_config vm2_pci_devs[VM2_CONFIG_PCI_DEV_NUM] = {
+	{
+		.emu_type = PCI_DEV_TYPE_HVEMUL,
+		.vbdf.value = UNASSIGNED_VBDF,
+		.vdev_ops = &vpci_ivshmem_ops,
+		.shm_region_name = IVSHMEM_SHM_REGION_0
+	},
 };

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/vbar_base.h

@@ -40,4 +40,7 @@
 #define ETHERNET_CONTROLLER_1_VBAR                    .vbar_base[0] = 0xa1100000UL, \
                                                       .vbar_base[3] = 0xa1120000UL
 
+#define IVSHMEM_DEVICE_0_VBAR                         .vbar_base[0] = 0x80000000UL, \
+                                                      .vbar_base[2] = 0x10000000cUL
+
 #endif /* VBAR_BASE_H_ */

misc/vm_configs/scenarios/hybrid_rt/whl-ipc-i5/whl-ipc-i5.config

@@ -8,6 +8,7 @@ CONFIG_LOW_RAM_SIZE=0x00010000
 CONFIG_SOS_RAM_SIZE=0x400000000
 CONFIG_UOS_RAM_SIZE=0x200000000
 CONFIG_STACK_SIZE=0x2000
+CONFIG_IVSHMEM_ENABLED=y
 CONFIG_GPU_SBDF=0x00000010
 CONFIG_UEFI_OS_LOADER_NAME=""
 CONFIG_SCHED_BVT=y