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hv: irq: fix "Procedure has more than one exit point"

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IEC 61508,ISO 26262 standards highly recommend single-exit rule.

Reduce the count of the "return entries".
Fix the violations which is comply with the cases list below:
1.Function has 2 return entries.
2.The first return entry is used to return the error code of
checking variable whether is valid.

Fix the violations in "if else" format.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Huihuang Shi 2018-11-28 10:23:59 +08:00 committed by lijinxia
parent 8dfb9bd9c0
commit c32d41a0be
2 changed files with 133 additions and 137 deletions
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86
hypervisor/arch/x86/ioapic.c
View File

@ -176,22 +176,22 @@ create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
union ioapic_rte rte; union ioapic_rte rte;
if (irq < NR_LEGACY_IRQ) { if (irq < NR_LEGACY_IRQ) {
return create_rte_for_legacy_irq(irq, vr); rte = create_rte_for_legacy_irq(irq, vr);
} else {
/* irq default masked, level trig */
rte.full = IOAPIC_RTE_INTMSET;
rte.full |= IOAPIC_RTE_TRGRLVL;
rte.full |= DEFAULT_DEST_MODE;
rte.full |= DEFAULT_DELIVERY_MODE;
rte.full |= (IOAPIC_RTE_INTVEC & (uint64_t)vr);
/* Fixed to active high */
rte.full |= IOAPIC_RTE_INTAHI;
/* Dest field */
rte.full |= ((uint64_t)ALL_CPUS_MASK << IOAPIC_RTE_DEST_SHIFT);
} }
/* irq default masked, level trig */
rte.full = IOAPIC_RTE_INTMSET;
rte.full |= IOAPIC_RTE_TRGRLVL;
rte.full |= DEFAULT_DEST_MODE;
rte.full |= DEFAULT_DELIVERY_MODE;
rte.full |= (IOAPIC_RTE_INTVEC & (uint64_t)vr);
/* Fixed to active high */
rte.full |= IOAPIC_RTE_INTAHI;
/* Dest field */
rte.full |= ((uint64_t)ALL_CPUS_MASK << IOAPIC_RTE_DEST_SHIFT);
return rte; return rte;
} }
@ -222,28 +222,24 @@ void ioapic_get_rte(uint32_t irq, union ioapic_rte *rte)
{ {
void *addr; void *addr;
if (!irq_is_gsi(irq)) { if (irq_is_gsi(irq)) {
return; addr = gsi_table[irq].addr;
ioapic_get_rte_entry(addr, gsi_table[irq].pin, rte);
} }
addr = gsi_table[irq].addr;
ioapic_get_rte_entry(addr, gsi_table[irq].pin, rte);
} }
void ioapic_set_rte(uint32_t irq, union ioapic_rte rte) void ioapic_set_rte(uint32_t irq, union ioapic_rte rte)
{ {
void *addr; void *addr;
if (!irq_is_gsi(irq)) { if (irq_is_gsi(irq)) {
return; addr = gsi_table[irq].addr;
ioapic_set_rte_entry(addr, gsi_table[irq].pin, rte);
dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
irq, gsi_table[irq].pin,
rte.full);
} }
addr = gsi_table[irq].addr;
ioapic_set_rte_entry(addr, gsi_table[irq].pin, rte);
dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%lx",
irq, gsi_table[irq].pin,
rte.full);
} }
bool irq_is_gsi(uint32_t irq) bool irq_is_gsi(uint32_t irq)
@ -253,11 +249,15 @@ bool irq_is_gsi(uint32_t irq)
uint8_t irq_to_pin(uint32_t irq) uint8_t irq_to_pin(uint32_t irq)
{ {
uint8_t ret;
if (irq_is_gsi(irq)) { if (irq_is_gsi(irq)) {
return gsi_table[irq].pin; ret = gsi_table[irq].pin;
} else { } else {
return IOAPIC_INVALID_PIN; ret = IOAPIC_INVALID_PIN;
} }
return ret;
} }
uint32_t pin_to_irq(uint8_t pin) uint32_t pin_to_irq(uint8_t pin)
@ -279,22 +279,20 @@ irq_gsi_mask_unmask(uint32_t irq, bool mask)
uint8_t pin; uint8_t pin;
union ioapic_rte rte; union ioapic_rte rte;
if (!irq_is_gsi(irq)) { if (irq_is_gsi(irq)) {
return; addr = gsi_table[irq].addr;
} pin = gsi_table[irq].pin;
addr = gsi_table[irq].addr; ioapic_get_rte_entry(addr, pin, &rte);
pin = gsi_table[irq].pin; if (mask) {
rte.full |= IOAPIC_RTE_INTMSET;
ioapic_get_rte_entry(addr, pin, &rte); } else {
if (mask) { rte.full &= ~IOAPIC_RTE_INTMASK;
rte.full |= IOAPIC_RTE_INTMSET; }
} else { ioapic_set_rte_entry(addr, pin, rte);
rte.full &= ~IOAPIC_RTE_INTMASK; dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
irq, pin, rte.full);
} }
ioapic_set_rte_entry(addr, pin, rte);
dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%lx",
irq, pin, rte.full);
} }
void gsi_mask_irq(uint32_t irq) void gsi_mask_irq(uint32_t irq)

184
hypervisor/arch/x86/irq.c
View File

@ -36,26 +36,28 @@ uint32_t alloc_irq_num(uint32_t req_irq)
{ {
uint32_t irq = req_irq; uint32_t irq = req_irq;
uint64_t rflags; uint64_t rflags;
uint32_t ret;
if ((irq >= NR_IRQS) && (irq != IRQ_INVALID)) { if ((irq >= NR_IRQS) && (irq != IRQ_INVALID)) {
pr_err("[%s] invalid req_irq %u", __func__, req_irq); pr_err("[%s] invalid req_irq %u", __func__, req_irq);
return IRQ_INVALID; ret = IRQ_INVALID;
}
spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
if (irq == IRQ_INVALID) {
/* if no valid irq num given, find a free one */
irq = (uint32_t)ffz64_ex(irq_alloc_bitmap, NR_IRQS);
}
if (irq >= NR_IRQS) {
irq = IRQ_INVALID;
} else { } else {
bitmap_set_nolock((uint16_t)(irq & 0x3FU), spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
irq_alloc_bitmap + (irq >> 6U)); if (irq == IRQ_INVALID) {
/* if no valid irq num given, find a free one */
irq = (uint32_t)ffz64_ex(irq_alloc_bitmap, NR_IRQS);
}
if (irq >= NR_IRQS) {
irq = IRQ_INVALID;
} else {
bitmap_set_nolock((uint16_t)(irq & 0x3FU),
irq_alloc_bitmap + (irq >> 6U));
}
spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
ret = irq;
} }
spinlock_irqrestore_release(&irq_alloc_spinlock, rflags); return ret;
return irq;
} }
/* /*
@ -66,15 +68,13 @@ void free_irq_num(uint32_t irq)
{ {
uint64_t rflags; uint64_t rflags;
if (irq >= NR_IRQS) { if (irq < NR_IRQS) {
return; if (!irq_is_gsi(irq)) {
} spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
(void)bitmap_test_and_clear_nolock((uint16_t)(irq & 0x3FU),
if (irq_is_gsi(irq) == false) { irq_alloc_bitmap + (irq >> 6U));
spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags); spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
(void)bitmap_test_and_clear_nolock((uint16_t)(irq & 0x3FU), }
irq_alloc_bitmap + (irq >> 6U));
spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
} }
} }
@ -89,43 +89,44 @@ uint32_t alloc_irq_vector(uint32_t irq)
uint32_t vr; uint32_t vr;
struct irq_desc *desc; struct irq_desc *desc;
uint64_t rflags; uint64_t rflags;
uint32_t ret;
if (irq >= NR_IRQS) { if (irq < NR_IRQS) {
pr_err("invalid irq[%u] to alloc vector", irq); desc = &irq_desc_array[irq];
return VECTOR_INVALID;
}
desc = &irq_desc_array[irq]; if (desc->vector != VECTOR_INVALID) {
if (vector_to_irq[desc->vector] == irq) {
if (desc->vector != VECTOR_INVALID) { /* statically binded */
if (vector_to_irq[desc->vector] == irq) { vr = desc->vector;
/* statically binded */ } else {
vr = desc->vector; pr_err("[%s] irq[%u]:vector[%u] mismatch",
} else { __func__, irq, desc->vector);
pr_err("[%s] irq[%u]:vector[%u] mismatch", vr = VECTOR_INVALID;
__func__, irq, desc->vector);
vr = VECTOR_INVALID;
}
} else {
/* alloc a vector between:
* VECTOR_DYNAMIC_START ~ VECTOR_DYNAMC_END
*/
spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
for (vr = VECTOR_DYNAMIC_START;
vr <= VECTOR_DYNAMIC_END; vr++) {
if (vector_to_irq[vr] == IRQ_INVALID) {
desc->vector = vr;
vector_to_irq[vr] = irq;
break;
} }
} else {
/* alloc a vector between:
* VECTOR_DYNAMIC_START ~ VECTOR_DYNAMC_END
*/
spinlock_irqsave_obtain(&irq_alloc_spinlock, &rflags);
for (vr = VECTOR_DYNAMIC_START;
vr <= VECTOR_DYNAMIC_END; vr++) {
if (vector_to_irq[vr] == IRQ_INVALID) {
desc->vector = vr;
vector_to_irq[vr] = irq;
break;
}
}
vr = (vr > VECTOR_DYNAMIC_END) ? VECTOR_INVALID : vr;
spinlock_irqrestore_release(&irq_alloc_spinlock, rflags);
} }
vr = (vr > VECTOR_DYNAMIC_END) ? VECTOR_INVALID : vr; ret = vr;
} else {
spinlock_irqrestore_release(&irq_alloc_spinlock, rflags); pr_err("invalid irq[%u] to alloc vector", irq);
ret = VECTOR_INVALID;
} }
return ret;
return vr;
} }
/* free the vector allocated via alloc_irq_vector() */ /* free the vector allocated via alloc_irq_vector() */
@ -226,22 +227,20 @@ void free_irq(uint32_t irq)
uint64_t rflags; uint64_t rflags;
struct irq_desc *desc; struct irq_desc *desc;
if (irq >= NR_IRQS) { if (irq < NR_IRQS) {
return; desc = &irq_desc_array[irq];
dev_dbg(ACRN_DBG_IRQ, "[%s] irq%d vr:0x%x",
__func__, irq, irq_to_vector(irq));
free_irq_vector(irq);
free_irq_num(irq);
spinlock_irqsave_obtain(&desc->lock, &rflags);
desc->action = NULL;
desc->priv_data = NULL;
desc->flags = IRQF_NONE;
spinlock_irqrestore_release(&desc->lock, rflags);
} }
desc = &irq_desc_array[irq];
dev_dbg(ACRN_DBG_IRQ, "[%s] irq%d vr:0x%x",
__func__, irq, irq_to_vector(irq));
free_irq_vector(irq);
free_irq_num(irq);
spinlock_irqsave_obtain(&desc->lock, &rflags);
desc->action = NULL;
desc->priv_data = NULL;
desc->flags = IRQF_NONE;
spinlock_irqrestore_release(&desc->lock, rflags);
} }
void set_irq_trigger_mode(uint32_t irq, bool is_level_triggered) void set_irq_trigger_mode(uint32_t irq, bool is_level_triggered)
@ -249,27 +248,28 @@ void set_irq_trigger_mode(uint32_t irq, bool is_level_triggered)
uint64_t rflags; uint64_t rflags;
struct irq_desc *desc; struct irq_desc *desc;
if (irq >= NR_IRQS) { if (irq < NR_IRQS) {
return; desc = &irq_desc_array[irq];
spinlock_irqsave_obtain(&desc->lock, &rflags);
if (is_level_triggered == true) {
desc->flags |= IRQF_LEVEL;
} else {
desc->flags &= ~IRQF_LEVEL;
}
spinlock_irqrestore_release(&desc->lock, rflags);
} }
desc = &irq_desc_array[irq];
spinlock_irqsave_obtain(&desc->lock, &rflags);
if (is_level_triggered == true) {
desc->flags |= IRQF_LEVEL;
} else {
desc->flags &= ~IRQF_LEVEL;
}
spinlock_irqrestore_release(&desc->lock, rflags);
} }
uint32_t irq_to_vector(uint32_t irq) uint32_t irq_to_vector(uint32_t irq)
{ {
uint32_t ret;
if (irq < NR_IRQS) { if (irq < NR_IRQS) {
return irq_desc_array[irq].vector; ret = irq_desc_array[irq].vector;
} else { } else {
return VECTOR_INVALID; ret = VECTOR_INVALID;
} }
return ret;
} }
static void handle_spurious_interrupt(uint32_t vector) static void handle_spurious_interrupt(uint32_t vector)
@ -435,16 +435,14 @@ static void disable_pic_irqs(void)
void init_default_irqs(uint16_t cpu_id) void init_default_irqs(uint16_t cpu_id)
{ {
if (cpu_id != BOOT_CPU_ID) { if (cpu_id == BOOT_CPU_ID) {
return; init_irq_descs();
/* we use ioapic only, disable legacy PIC */
disable_pic_irqs();
setup_ioapic_irqs();
init_softirq();
} }
init_irq_descs();
/* we use ioapic only, disable legacy PIC */
disable_pic_irqs();
setup_ioapic_irqs();
init_softirq();
} }
void interrupt_init(uint16_t pcpu_id) void interrupt_init(uint16_t pcpu_id)