mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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hv: emulate cpuids and MSRs for VHWP
Changes made by this patch includes:
1. Emulate HWP and pstate MSRs/CPUIDs. Those are exposed to guest when
the GUEST_FLAG_VHWP is set:
- CPUID[6].EAX[7,9,10]: MSR_IA32_PM_ENABLE(enabled by hv, always read
1), MSR_IA32_HWP_CAPABILITIES, MSR_IA32_HWP_REQUEST,
MSR_IA32_HWP_STATUS,
- CPUID[6].ECX[0]: MSR_IA32_MPERF, MSR_IA32_APERF
- MSR_IA32_PERF_STATUS(read as base frequency when not owning pCPU)
- MSR_IA32_PERF_CTL(ignore writes)
2. Always hide HWP interrupt and package control MSRs/CPUIDs:
- CPUID[6].EAX[8]: MSR_IA32_HWP_INTERRUPT(currently ACRN is not able
to deliver thermal LVT virtual interrupt to guests)
- CPUID[6].EAX[11,22]: MSR_IA32_HWP_REQUEST_PKG, MSR_IA32_HWP_CTL
Tracked-On: #8414
Signed-off-by: Wu Zhou <wu.zhou@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Wu Zhou
acrnsi-robot
parent
2edf141047
commit
c5d019b836
@ -115,11 +115,10 @@ static void init_vcpuid_entry(uint32_t leaf, uint32_t subleaf,
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entry->flags = flags;
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switch (leaf) {
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case 0x06U:
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cpuid_subleaf(leaf, subleaf, &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
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entry->eax &= ~(CPUID_EAX_HWP | CPUID_EAX_HWP_N | CPUID_EAX_HWP_AW | CPUID_EAX_HWP_EPP | CPUID_EAX_HWP_PLR);
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entry->ecx &= ~CPUID_ECX_HCFC;
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/* Always hide package level HWP controls and HWP interrupt*/
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entry->eax &= ~(CPUID_EAX_HWP_CTL | CPUID_EAX_HWP_PLR | CPUID_EAX_HWP_N);
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break;
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case 0x07U:
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@ -548,6 +547,15 @@ int32_t set_vcpuid_entries(struct acrn_vm *vm)
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/* MONITOR/MWAIT */
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case 0x05U:
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break;
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case 0x06U:
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init_vcpuid_entry(i, 0U, CPUID_CHECK_SUBLEAF, &entry);
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/* For VMs without vhwp, HWP and HCFC are always hidden. */
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if (!is_vhwp_configured(vm)) {
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entry.eax &= ~(CPUID_EAX_HWP | CPUID_EAX_HWP_AW | CPUID_EAX_HWP_EPP);
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entry.ecx &= ~CPUID_ECX_HCFC;
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}
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result = set_vcpuid_entry(vm, &entry);
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break;
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case 0x07U:
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init_vcpuid_entry(i, 0U, CPUID_CHECK_SUBLEAF, &entry);
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if (entry.eax != 0U) {
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@ -79,6 +79,13 @@ static uint32_t emulated_guest_msrs[NUM_EMULATED_MSRS] = {
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MSR_PLATFORM_INFO,
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MSR_IA32_PM_ENABLE,
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MSR_IA32_HWP_CAPABILITIES,
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MSR_IA32_HWP_REQUEST,
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MSR_IA32_HWP_STATUS,
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MSR_IA32_MPERF,
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MSR_IA32_APERF,
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/* VMX: CPUID.01H.ECX[5] */
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#ifdef CONFIG_NVMX_ENABLED
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LIST_OF_VMX_MSRS,
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@ -260,28 +267,19 @@ static const uint32_t unsupported_msrs[] = {
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MSR_IA32_PL3_SSP,
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MSR_IA32_INTERRUPT_SSP_TABLE_ADDR,
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/* HWP disabled:
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* CPUID.06H.EAX[7]
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* CPUID.06H.EAX[9]
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* CPUID.06H:EAX[10]
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*/
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MSR_IA32_PM_ENABLE,
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MSR_IA32_HWP_CAPABILITIES,
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MSR_IA32_HWP_REQUEST,
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MSR_IA32_HWP_STATUS,
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/* HWP_Notification disabled:
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* CPUID.06H:EAX[8]
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*/
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MSR_IA32_HWP_INTERRUPT,
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/* HWP_package_level disabled:
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* CPUID.06H:EAX[11]
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/*
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* HWP package ctrl disabled:
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* CPUID.06H.EAX[11] (MSR_IA32_HWP_REQUEST_PKG)
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* CPUID.06H.EAX[22] (MSR_IA32_HWP_CTL)
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*/
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MSR_IA32_HWP_REQUEST_PKG,
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/* Hardware Coordination Feedback Capability disabled:
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* CPUID.06H:ECX[0]
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MSR_IA32_HWP_CTL,
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/*
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* HWP interrupt disabled:
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* CPUID.06H.EAX[8]
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*/
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MSR_IA32_MPERF,
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MSR_IA32_APERF,
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MSR_IA32_HWP_INTERRUPT,
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};
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/* emulated_guest_msrs[] shares same indexes with array vcpu->arch->guest_msrs[] */
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@ -672,7 +670,11 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
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}
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case MSR_IA32_PERF_STATUS:
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{
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v = get_perf_status();
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if (is_vhwp_configured(vcpu->vm)) {
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v = msr_read(msr);
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} else {
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v = get_perf_status();
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}
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break;
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}
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case MSR_IA32_PERF_CTL:
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@ -680,6 +682,20 @@ int32_t rdmsr_vmexit_handler(struct acrn_vcpu *vcpu)
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v = vcpu_get_guest_msr(vcpu, MSR_IA32_PERF_CTL);
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break;
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}
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case MSR_IA32_PM_ENABLE:
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case MSR_IA32_HWP_CAPABILITIES:
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case MSR_IA32_HWP_REQUEST:
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case MSR_IA32_HWP_STATUS:
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case MSR_IA32_MPERF:
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case MSR_IA32_APERF:
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{
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if (is_vhwp_configured(vcpu->vm)) {
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v = msr_read(msr);
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} else {
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err = -EACCES;
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}
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break;
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}
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case MSR_IA32_PAT:
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{
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/*
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@ -1059,6 +1075,48 @@ int32_t wrmsr_vmexit_handler(struct acrn_vcpu *vcpu)
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vcpu_set_guest_msr(vcpu, MSR_IA32_PERF_CTL, v);
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break;
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}
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case MSR_IA32_PM_ENABLE:
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{
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if (!is_vhwp_configured(vcpu->vm)) {
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err = -EACCES;
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}
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/* Set by HV. Writing from guests will have no effect */
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break;
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}
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case MSR_IA32_HWP_CAPABILITIES:
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{
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/* RO */
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break;
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}
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case MSR_IA32_HWP_REQUEST:
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{
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if (is_vhwp_configured(vcpu->vm) &&
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((v & (MSR_IA32_HWP_REQUEST_RSV_BITS | MSR_IA32_HWP_REQUEST_PKG_CTL)) == 0)) {
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msr_write(msr, v);
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} else {
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err = -EACCES;
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}
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break;
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}
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case MSR_IA32_HWP_STATUS:
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{
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if (is_vhwp_configured(vcpu->vm) && ((v & MSR_IA32_HWP_STATUS_RSV_BITS) == 0)) {
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msr_write(msr, v);
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} else {
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err = -EACCES;
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}
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break;
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}
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case MSR_IA32_MPERF:
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case MSR_IA32_APERF:
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{
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if (is_vhwp_configured(vcpu->vm)) {
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msr_write(msr, v);
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} else {
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err = -EACCES;
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}
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break;
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}
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case MSR_IA32_PAT:
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{
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err = write_pat_msr(vcpu, v);
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@ -84,6 +84,8 @@
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#define CPUID_EAX_HWP_EPP (1U<<10U)
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/* CPUID.06H:EAX.HWP_Package_Level_Request */
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#define CPUID_EAX_HWP_PLR (1U<<11U)
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/* CPUID.06H:EAX.HWP_control */
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#define CPUID_EAX_HWP_CTL (1U<<22U)
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/* CPUID.06H:ECX.Hardware_Coordination_Feedback_Capability */
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#define CPUID_ECX_HCFC (1U<<0U)
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/* CPUID.07H:EBX.FSGSBASE*/
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@ -175,7 +175,7 @@ enum reset_mode;
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#define SECURE_WORLD 1
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#define NUM_WORLD_MSRS 2U
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#define NUM_COMMON_MSRS 25U
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#define NUM_COMMON_MSRS 31U
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#ifdef CONFIG_VCAT_ENABLED
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#define NUM_CAT_L2_MSRS MAX_CACHE_CLOS_NUM_ENTRIES
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@ -294,6 +294,7 @@
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#define MSR_IA32_HWP_INTERRUPT 0x00000773U
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#define MSR_IA32_HWP_REQUEST 0x00000774U
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#define MSR_IA32_HWP_PECI_REQUEST_INFO 0x00000775U
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#define MSR_IA32_HWP_CTL 0x00000776U
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#define MSR_IA32_HWP_STATUS 0x00000777U
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#define MSR_IA32_EXT_XAPICID 0x00000802U
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@ -679,4 +680,8 @@ void update_msr_bitmap_x2apic_passthru(struct acrn_vcpu *vcpu);
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#define MSR_PLATFORM_INFO_MIN_OPERATING_RATIO_MASK (0x00ff000000000000UL) /* 55:48 */
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#define MSR_PLATFORM_INFO_SAMPLE_PART (1UL << 27U)
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#define MSR_IA32_HWP_STATUS_RSV_BITS (~0x3DUL)
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#define MSR_IA32_HWP_REQUEST_RSV_BITS (0x7FFF80000000000UL)
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#define MSR_IA32_HWP_REQUEST_PKG_CTL (1UL << 42U)
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#endif /* MSR_H */
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