From c69dab0a1153a0d74e476ead96f29e235fa57b03 Mon Sep 17 00:00:00 2001 From: Jian Jun Chen Date: Tue, 26 Feb 2019 01:18:12 +0000 Subject: [PATCH] hv: add support of EPT mapping of high MMIO Enlarge hypervisor BSS section to support EPT mapping of additional 1G address space. This is used to support 64bit PCI bar whose address is strictly above 4G. Tracked-On: #2577 Signed-off-by: Jian Jun Chen Reviewed-by: Yu Wang Reviewed-by: Li, Fei1 Acked-by: Eddie Dong --- hypervisor/arch/x86/Kconfig | 4 ++-- hypervisor/include/arch/x86/page.h | 13 +++++++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/hypervisor/arch/x86/Kconfig b/hypervisor/arch/x86/Kconfig index 9a9db58b3..b928250af 100644 --- a/hypervisor/arch/x86/Kconfig +++ b/hypervisor/arch/x86/Kconfig @@ -243,8 +243,8 @@ config HV_RAM_START config HV_RAM_SIZE hex "Size of the RAM region used by the hypervisor" - default 0x07800000 if PLATFORM_SBL - default 0x0b000000 if PLATFORM_UEFI + default 0x08000000 if PLATFORM_SBL + default 0x0b800000 if PLATFORM_UEFI help A 64-bit integer indicating the size of RAM used by the hypervisor. It is ensured at link time that the footprint of the hypervisor diff --git a/hypervisor/include/arch/x86/page.h b/hypervisor/include/arch/x86/page.h index 62507829a..6e4c0a7bf 100644 --- a/hypervisor/include/arch/x86/page.h +++ b/hypervisor/include/arch/x86/page.h @@ -14,13 +14,22 @@ /* size of the low MMIO address space: 2GB */ #define PLATFORM_LO_MMIO_SIZE 0x80000000UL +/* size of the high MMIO address space: 1GB */ +#define PLATFORM_HI_MMIO_SIZE 0x40000000UL + #define PML4_PAGE_NUM(size) 1UL #define PDPT_PAGE_NUM(size) (((size) + PML4E_SIZE - 1UL) >> PML4E_SHIFT) #define PD_PAGE_NUM(size) (((size) + PDPTE_SIZE - 1UL) >> PDPTE_SHIFT) #define PT_PAGE_NUM(size) (((size) + PDE_SIZE - 1UL) >> PDE_SHIFT) -/* The size of the guest physical address space, covered by the EPT page table of a VM */ -#define EPT_ADDRESS_SPACE(size) (((size) != 0UL) ? ((size) + PLATFORM_LO_MMIO_SIZE) : 0UL) +/* + * The size of the guest physical address space, covered by the EPT page table of a VM. + * With the assumptions: + * - The GPA of DRAM & MMIO are contiguous. + * - Guest OS won't re-program device MMIO bars to the address not covered by + * this EPT_ADDRESS_SPACE. + */ +#define EPT_ADDRESS_SPACE(size) (((size) != 0UL) ? ((size) + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE) : 0UL) #define TRUSTY_PML4_PAGE_NUM(size) (1UL) #define TRUSTY_PDPT_PAGE_NUM(size) (1UL)