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hv: Switch APICv from MMIO to MSR for x2APIC mode of guest vLAPIC

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When guest switches from xAPIC mode to x2APIC mode of vLAPIC operation,
MSRs are used to access vLAPIC. This patch adds APICv support for
MSR accesses to vLAPIC. Switching from xAPIC to x2APIC is supported via
APIC BASE MSR. Other modifications like disabling and switching back to
xAPIC are not supported.

Tracked-On: #1626
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Xu Anthony <anthony.xu@intel.com>
This commit is contained in:
Sainath Grandhi
2018-11-01 15:21:46 -07:00
committed by lijinxia
parent cf4d191272
commit c85e35d31b
4 changed files with 33 additions and 0 deletions
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hypervisor/include/arch/x86/vmx.h
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@@ -464,6 +464,7 @@ int vmx_wrmsr_pat(struct vcpu *vcpu, uint64_t value);
void vmx_write_cr0(struct vcpu *vcpu, uint64_t cr0);
void vmx_write_cr4(struct vcpu *vcpu, uint64_t cr4);
bool is_vmx_disabled(void);
void switch_apicv_mode_x2apic(struct vcpu *vcpu);
static inline enum vm_cpu_mode get_vcpu_mode(const struct vcpu *vcpu)
{