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Add APIC ACCESS VMexit handler

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Update 'apic_access_exit_handler()' function to emulate
guest instruments to read/write guest's lapic registers page

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Yonghua Huang 2018-03-21 01:05:50 +08:00 committed by Anthony Xu
parent 7ce4248e34
commit c8dc56e08b
4 changed files with 44 additions and 4 deletions
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30
arch/x86/guest/vlapic.c
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@ -37,6 +37,9 @@
#include <bsp_extern.h> #include <bsp_extern.h>
#include <hv_debug.h> #include <hv_debug.h>
#include "instr_emul_wrapper.h"
#include "instr_emul.h"
#include "time.h" #include "time.h"
#include "vlapic_priv.h" #include "vlapic_priv.h"
@ -2331,9 +2334,32 @@ apicv_inject_pir(struct vlapic *vlapic)
} }
} }
int apicv_access_exit_handler(__unused struct vcpu *vcpu) int apic_access_exit_handler(struct vcpu *vcpu)
{ {
TRACE_2L(TRC_VMEXIT_APICV_ACCESS, 0, 0); bool ret;
int access_type, offset;
uint64_t qual;
struct vlapic *vlapic;
qual = vcpu->arch_vcpu.exit_qualification;
access_type = APIC_ACCESS_TYPE(qual);
/*parse offset if linear access*/
if (access_type <= 3)
offset = APIC_ACCESS_OFFSET(qual);
vlapic = vcpu->arch_vcpu.vlapic;
analyze_instruction(vcpu, &vcpu->mmio);
if (access_type == 1) {
if (!emulate_instruction(vcpu, &vcpu->mmio))
vlapic_write(vlapic, 1, offset, vcpu->mmio.value, &ret);
} else if (access_type == 0) {
vlapic_read(vlapic, 1, offset, &vcpu->mmio.value, &ret);
emulate_instruction(vcpu, &vcpu->mmio);
}
TRACE_2L(TRC_VMEXIT_APICV_ACCESS, qual, (uint64_t)vlapic);
return 0; return 0;
} }

2
arch/x86/vmexit.c
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@ -125,7 +125,7 @@ static const struct vm_exit_dispatch dispatch_table[] = {
[VMX_EXIT_REASON_TPR_BELOW_THRESHOLD] = { [VMX_EXIT_REASON_TPR_BELOW_THRESHOLD] = {
.handler = unhandled_vmexit_handler}, .handler = unhandled_vmexit_handler},
[VMX_EXIT_REASON_APIC_ACCESS] = { [VMX_EXIT_REASON_APIC_ACCESS] = {
.handler = apicv_access_exit_handler, .handler = apic_access_exit_handler,
.need_exit_qualification = 1}, .need_exit_qualification = 1},
[VMX_EXIT_REASON_VIRTUALIZED_EOI] = { [VMX_EXIT_REASON_VIRTUALIZED_EOI] = {
.handler = apicv_virtualized_eoi_exit_handler, .handler = apicv_virtualized_eoi_exit_handler,

2
include/arch/x86/guest/vlapic.h
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@ -125,7 +125,7 @@ uint64_t apicv_get_apic_access_addr(struct vm *vm);
uint64_t apicv_get_apic_page_addr(struct vlapic *vlapic); uint64_t apicv_get_apic_page_addr(struct vlapic *vlapic);
bool vlapic_apicv_enabled(struct vcpu *vcpu); bool vlapic_apicv_enabled(struct vcpu *vcpu);
void apicv_inject_pir(struct vlapic *vlapic); void apicv_inject_pir(struct vlapic *vlapic);
int apicv_access_exit_handler(struct vcpu *vcpu); int apic_access_exit_handler(struct vcpu *vcpu);
int apicv_write_exit_handler(struct vcpu *vcpu); int apicv_write_exit_handler(struct vcpu *vcpu);
int apicv_virtualized_eoi_exit_handler(struct vcpu *vcpu); int apicv_virtualized_eoi_exit_handler(struct vcpu *vcpu);

14
include/arch/x86/vmx.h
View File

@ -351,6 +351,20 @@
#define VMX_INT_TYPE_HW_EXP 3 #define VMX_INT_TYPE_HW_EXP 3
#define VMX_INT_TYPE_SW_EXP 6 #define VMX_INT_TYPE_SW_EXP 6
/*VM exit qulifications for APIC-access
* Access type:
* 0 = linear access for a data read during instruction execution
* 1 = linear access for a data write during instruction execution
* 2 = linear access for an instruction fetch
* 3 = linear access (read or write) during event delivery
* 10 = guest-physical access during event delivery
* 15 = guest-physical access for an instructon fetch or during
* instruction execution
*/
#define APIC_ACCESS_TYPE(qual) (((qual) >> 12) & 0xF)
#define APIC_ACCESS_OFFSET(qual) ((qual) & 0xFFF)
#define VM_SUCCESS 0 #define VM_SUCCESS 0
#define VM_FAIL -1 #define VM_FAIL -1