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https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-21 13:08:42 +00:00
DM USB: xHCI: refine xHCI extended capability related functions.
Every platform should have their own xHCI specific extended capabilities, but the current xHCI DM is not scalable for them. This patch refines related logic to make it scalable. Current code only support 4 registers(4*32) as basic extended capabilites. Base on this new implementation, the mmio range from excapoff to regsend will cover real excap size according to the cap parameter. Change-Id: Ic55a4494e090ec255939cdb8f32950e3c8a66082 Signed-off-by: Liang Yang <liang3.yang@intel.com> Reviewed-by: Xiaoguang Wu <xiaoguang.wu@intel.com> Reviewed-by: Yu Wang <yu1.wang@intel.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com>
This commit is contained in:
YanLiang
lijinxia
parent
ba1b034e1e
commit
c91590ccfd
134
devicemodel/hw/pci/xhci.c
Normal file → Executable file
134
devicemodel/hw/pci/xhci.c
Normal file → Executable file
@ -211,6 +211,51 @@ struct pci_xhci_rtsregs {
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uint32_t event_pcs; /* producer cycle state flag */
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};
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struct pci_xhci_excap_ptr {
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uint8_t cap_id;
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uint8_t cap_ptr;
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} __attribute__((packed));
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struct pci_xhci_excap_prot {
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struct pci_xhci_excap_ptr excap_ptr;
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uint8_t rev_min;
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uint8_t rev_maj;
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char string[4];
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uint8_t port_off;
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uint8_t port_cnt;
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uint16_t psic_prot_def;
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uint32_t reserve;
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} __attribute__((packed));
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struct pci_xhci_excap {
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uint32_t start;
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uint32_t end;
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void *data;
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};
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static DEFINE_EXCP_PROT(u2_prot,
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0x08,
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2,
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XHCI_MAX_DEVS/2 + 1,
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XHCI_MAX_DEVS/2);
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static DEFINE_EXCP_PROT(u3_prot,
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0x14,
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3,
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1,
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XHCI_MAX_DEVS/2);
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/*
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* default xhci extended capabilities
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* excap start excap end register value
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* 0x8000 0x8010 0x02000802
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* 0x8020 0x8030 0x03001402
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*/
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struct pci_xhci_excap excap_group_dft[] = {
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{0x8000, 0x8010, &excap_u2_prot},
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{0x8020, 0x8030, &excap_u3_prot},
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{EXCAP_GROUP_END, EXCAP_GROUP_END, EXCAP_GROUP_NULL}
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};
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struct pci_xhci_vdev;
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/*
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@ -245,6 +290,7 @@ struct pci_xhci_vdev {
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uint32_t rtsoff; /* runtime register space offset */
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uint32_t hccparams2; /* capability parameters 2 */
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uint32_t excapoff; /* ext-capability registers offset */
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uint32_t regsend; /* end of configuration registers */
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struct pci_xhci_opregs opregs;
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@ -255,6 +301,7 @@ struct pci_xhci_vdev {
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struct pci_xhci_dev_emu **slots; /* slots assigned from 1 */
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int ndevices;
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void *excap_ptr;
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int usb2_port_start;
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int usb3_port_start;
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uint8_t *native_assign_ports[USB_NATIVE_NUM_BUS];
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@ -2683,7 +2730,7 @@ pci_xhci_write(struct vmctx *ctx,
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pci_xhci_hostop_write(xdev, offset, value);
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else if (offset < xdev->rtsoff)
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pci_xhci_dbregs_write(xdev, offset, value);
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else if (offset < xdev->regsend)
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else if (offset < xdev->excapoff)
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pci_xhci_rtsregs_write(xdev, offset, value);
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else
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UPRINTF(LWRN, "write invalid offset %ld\r\n", offset);
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@ -2838,48 +2885,33 @@ pci_xhci_rtsregs_read(struct pci_xhci_vdev *xdev, uint64_t offset)
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}
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static uint64_t
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pci_xhci_xecp_read(struct pci_xhci_vdev *xdev, uint64_t offset)
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pci_xhci_excap_read(struct pci_xhci_vdev *xdev, uint64_t offset)
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{
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uint32_t value;
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uint32_t value = 0;
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uint32_t off = offset;
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struct pci_xhci_excap *excap;
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offset -= xdev->regsend;
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value = 0;
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assert(xdev);
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switch (offset) {
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case 0:
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/* rev major | rev minor | next-cap | cap-id */
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value = (0x02 << 24) | (4 << 8) | XHCI_ID_PROTOCOLS;
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break;
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case 4:
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/* name string = "USB" */
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value = 0x20425355;
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break;
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case 8:
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/* psic | proto-defined | compat # | compat offset */
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value = ((XHCI_MAX_DEVS/2) << 8) | xdev->usb2_port_start;
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break;
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case 12:
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break;
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case 16:
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/* rev major | rev minor | next-cap | cap-id */
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value = (0x03 << 24) | XHCI_ID_PROTOCOLS;
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break;
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case 20:
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/* name string = "USB" */
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value = 0x20425355;
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break;
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case 24:
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/* psic | proto-defined | compat # | compat offset */
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value = ((XHCI_MAX_DEVS/2) << 8) | xdev->usb3_port_start;
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break;
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case 28:
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break;
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default:
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UPRINTF(LDBG, "xecp invalid offset 0x%lx\r\n", offset);
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excap = xdev->excap_ptr;
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while (excap && excap->start != EXCAP_GROUP_END) {
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if (off >= excap->start && off < excap->end)
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break;
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excap++;
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}
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UPRINTF(LDBG, "xecp read offset 0x%lx -> 0x%x\r\n", offset, value);
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if (!excap || excap->start == EXCAP_GROUP_END) {
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UPRINTF(LWRN, "extended capability 0x%lx can't be found\r\n",
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offset);
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return value;
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}
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if (excap->start != EXCAP_GROUP_END) {
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off -= excap->start;
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memcpy(&value, (uint32_t *)excap->data + off / 4,
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sizeof(uint32_t));
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}
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return value;
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}
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@ -2906,10 +2938,10 @@ pci_xhci_read(struct vmctx *ctx,
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value = pci_xhci_hostop_read(xdev, offset);
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else if (offset < xdev->rtsoff)
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value = pci_xhci_dbregs_read(xdev, offset);
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else if (offset < xdev->regsend)
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else if (offset < xdev->excapoff)
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value = pci_xhci_rtsregs_read(xdev, offset);
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else if (offset < (xdev->regsend + 4*32))
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value = pci_xhci_xecp_read(xdev, offset);
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else if (offset < xdev->regsend)
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value = pci_xhci_excap_read(xdev, offset);
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else {
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value = 0;
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UPRINTF(LDBG, "read invalid offset %ld\r\n", offset);
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@ -3327,6 +3359,7 @@ static int
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pci_xhci_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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{
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struct pci_xhci_vdev *xdev;
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struct pci_xhci_excap *excap;
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int error;
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if (xhci_in_use) {
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@ -3348,6 +3381,8 @@ pci_xhci_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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xdev->usb2_port_start = (XHCI_MAX_DEVS/2) + 1;
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xdev->usb3_port_start = 1;
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xdev->excap_ptr = excap_group_dft;
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/* discover devices */
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error = pci_xhci_parse_opts(xdev, opts);
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if (error < 0)
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@ -3398,14 +3433,19 @@ pci_xhci_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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pci_xhci_reset(xdev);
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/* only 1 intrpter */
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xdev->regsend = xdev->rtsoff + 0x20 + 32;
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excap = xdev->excap_ptr;
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xdev->excapoff = excap->start;
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while (excap && excap->start != EXCAP_GROUP_END)
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excap++;
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xdev->regsend = (excap - 1)->end;
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/*
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* Set extended capabilities pointer to be after regsend;
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* value of xecp field is 32-bit offset.
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* value of excap field is 32-bit offset.
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*/
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xdev->hccparams1 |= XHCI_SET_HCCP1_XECP(xdev->regsend/4);
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xdev->hccparams1 |= XHCI_SET_HCCP1_XECP(XHCI_EXCAP_PTR);
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pci_set_cfgdata16(dev, PCIR_DEVICE, 0x1E31);
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pci_set_cfgdata16(dev, PCIR_VENDOR, 0x8086);
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@ -3416,9 +3456,9 @@ pci_xhci_init(struct vmctx *ctx, struct pci_vdev *dev, char *opts)
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pci_emul_add_msicap(dev, 1);
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/* regsend + xecp registers */
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pci_emul_alloc_bar(dev, 0, PCIBAR_MEM32, xdev->regsend + 4*32);
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UPRINTF(LDBG, "pci_emu_alloc: %d\r\n", xdev->regsend + 4*32);
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/* regsend registers */
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pci_emul_alloc_bar(dev, 0, PCIBAR_MEM32, xdev->regsend);
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UPRINTF(LDBG, "pci_emu_alloc: %d\r\n", xdev->regsend);
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pci_lintr_request(dev);
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16
devicemodel/include/xhci.h
Normal file → Executable file
16
devicemodel/include/xhci.h
Normal file → Executable file
@ -86,6 +86,22 @@ enum {
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#define XHCI_TD_ALIGN 64 /* bytes */
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#define XHCI_PAGE_SIZE 4096 /* bytes */
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/* xHCI extended capability supported protocol fileds */
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#define DEFINE_EXCP_PROT(name, next_ptr, revmaj, portoff, portcnt) \
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struct pci_xhci_excap_prot excap_##name = { \
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{ \
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.cap_id = XHCI_ID_PROTOCOLS, \
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.cap_ptr = next_ptr \
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}, \
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.rev_min = 0x00, \
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.rev_maj = revmaj, \
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.string = "USB"#revmaj, \
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.port_off = portoff, \
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.port_cnt = portcnt, \
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.psic_prot_def = 0x00, \
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.reserve = 0x00 \
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}
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struct xhci_slot_ctx {
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volatile uint32_t dwSctx0;
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#define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF)
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11
devicemodel/include/xhcireg.h
Normal file → Executable file
11
devicemodel/include/xhcireg.h
Normal file → Executable file
@ -228,6 +228,17 @@
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#define XHCI_ID_MSG_IRQ 0x0005
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#define XHCI_ID_USB_LOCAL_MEM 0x0006
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/*
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* xHCI extended capability pointer in HCCPARAMS1.
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* The excap offset is calculated by left shift 2
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* bits which equals 0x8000
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*/
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#define XHCI_EXCAP_PTR 0x2000
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/* xHCI extended capability group end marker */
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#define EXCAP_GROUP_END 0xFFFF
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#define EXCAP_GROUP_NULL NULL
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/* XHCI register R/W wrappers */
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#define XREAD1(sc, what, a) \
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bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \
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