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hv/config_tools: amend the struct acrn_vm_config to make it compatible with vCAT

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For vCAT, it may need to store more than MAX_VCPUS_PER_VM of closids,
change clos in vm_config.h to a pointer to accommodate this situation

Rename clos to pclosids

pclosids now is a pointer to an array of physical CLOSIDs that is defined
in vm_configurations.c by vmconfig. The number of elements in the array
must be equal to the value given by num_pclosids

Add max_type_pcbm (type: l2 or l3) to struct acrn_vm_config, which stores a bitmask
that selects/covers all the physical cache ways assigned to the VM

Change vmsr.c to accommodate this amended data structure

Change the config-tools to generate vm_configurations.c, and fill in the num_closids
and clos pointers based on the information from the scenario file.

Now vm_configurations.c.xsl generates all the clos related code so remove the same
code from misc_cfg.h.xsl.

Examples:

  Scenario file:

  <RDT>
    <RDT_ENABLED>y</RDT_ENABLED>
    <CDP_ENABLED>n</CDP_ENABLED>
    <VCAT_ENABLED>y</VCAT_ENABLED>
    <CLOS_MASK>0x7ff</CLOS_MASK>
    <CLOS_MASK>0x7ff</CLOS_MASK>
    <CLOS_MASK>0x7ff</CLOS_MASK>
    <CLOS_MASK>0xff800</CLOS_MASK>
    <CLOS_MASK>0xff800</CLOS_MASK>
    <CLOS_MASK>0xff800</CLOS_MASK>
    <CLOS_MASK>0xff800</CLOS_MASK>
    <CLOS_MASK>0xff800</CLOS_MASK>
  /RDT>

  <vm id="0">
   <guest_flags>
     <guest_flag>GUEST_FLAG_VCAT_ENABLED</guest_flag>
   </guest_flags>
   <clos>
     <vcpu_clos>3</vcpu_clos>
     <vcpu_clos>4</vcpu_clos>
     <vcpu_clos>5</vcpu_clos>
     <vcpu_clos>6</vcpu_clos>
     <vcpu_clos>7</vcpu_clos>
   </clos>
  </vm>

  <vm id="1">
   <clos>
     <vcpu_clos>1</vcpu_clos>
     <vcpu_clos>2</vcpu_clos>
   </clos>
  </vm>

 vm_configurations.c (generated by config-tools) with the above vCAT config:

  static uint16_t vm0_vcpu_clos[5U] = {3U, 4U, 5U, 6U, 7U};
  static uint16_t vm1_vcpu_clos[2U] = {1U, 2U};

  struct acrn_vm_config vm_configs[CONFIG_MAX_VM_NUM] = {
  {
  .guest_flags = (GUEST_FLAG_VCAT_ENABLED),
  .pclosids = vm0_vcpu_clos,
  .num_pclosids = 5U,
  .max_l3_pcbm = 0xff800U,
  },
  {
  .pclosids = vm1_vcpu_clos,
  .num_pclosids = 2U,
  },
  };

Tracked-On: #5917
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
dongshen
2021-09-14 19:31:57 -07:00
committed by wenlingz
parent 3ddcbd424f
commit cb2bb78b6f
6 changed files with 95 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
hypervisor/arch/x86/guest/vmsr.c
View File

@@ -305,24 +305,32 @@ static void intercept_x2apic_msrs(uint8_t *msr_bitmap_arg, uint32_t mode)
}
/**
* @pre vcpu != NULL
* @pre vcpu != NULL && vcpu->vm != NULL && vcpu->vm->vm_id < CONFIG_MAX_VM_NUM
* @pre (is_platform_rdt_capable() == false()) || (is_platform_rdt_capable() && get_vm_config(vcpu->vm->vm_id)->pclosids != NULL)
*/
static void prepare_auto_msr_area (struct acrn_vcpu *vcpu)
static void prepare_auto_msr_area(struct acrn_vcpu *vcpu)
{
struct acrn_vm_config *cfg = get_vm_config(vcpu->vm->vm_id);
uint16_t vcpu_clos = cfg->clos[vcpu->vcpu_id];
vcpu->arch.msr_area.count = 0U;
/* only load/restore MSR IA32_PQR_ASSOC when hv and guest have differnt settings */
if (is_platform_rdt_capable() && (vcpu_clos != hv_clos)) {
vcpu->arch.msr_area.guest[MSR_AREA_IA32_PQR_ASSOC].msr_index = MSR_IA32_PQR_ASSOC;
vcpu->arch.msr_area.guest[MSR_AREA_IA32_PQR_ASSOC].value = clos2pqr_msr(vcpu_clos);
vcpu->arch.msr_area.host[MSR_AREA_IA32_PQR_ASSOC].msr_index = MSR_IA32_PQR_ASSOC;
vcpu->arch.msr_area.host[MSR_AREA_IA32_PQR_ASSOC].value = clos2pqr_msr(hv_clos);
vcpu->arch.msr_area.count++;
pr_acrnlog("switch clos for VM %u vcpu_id %u, host 0x%x, guest 0x%x",
vcpu->vm->vm_id, vcpu->vcpu_id, hv_clos, vcpu_clos);
if (is_platform_rdt_capable()) {
struct acrn_vm_config *cfg = get_vm_config(vcpu->vm->vm_id);
uint16_t vcpu_clos;
ASSERT(cfg->pclosids != NULL, "error, cfg->pclosids is NULL");
vcpu_clos = cfg->pclosids[vcpu->vcpu_id%cfg->num_pclosids];
/* RDT: only load/restore MSR_IA32_PQR_ASSOC when hv and guest have different settings */
if (vcpu_clos != hv_clos) {
vcpu->arch.msr_area.guest[MSR_AREA_IA32_PQR_ASSOC].msr_index = MSR_IA32_PQR_ASSOC;
vcpu->arch.msr_area.guest[MSR_AREA_IA32_PQR_ASSOC].value = clos2pqr_msr(vcpu_clos);
vcpu->arch.msr_area.host[MSR_AREA_IA32_PQR_ASSOC].msr_index = MSR_IA32_PQR_ASSOC;
vcpu->arch.msr_area.host[MSR_AREA_IA32_PQR_ASSOC].value = clos2pqr_msr(hv_clos);
vcpu->arch.msr_area.count++;
pr_acrnlog("switch clos for VM %u vcpu_id %u, host 0x%x, guest 0x%x",
vcpu->vm->vm_id, vcpu->vcpu_id, hv_clos, vcpu_clos);
}
}
}
@@ -392,7 +400,7 @@ void init_msr_emulation(struct acrn_vcpu *vcpu)
pr_dbg("VMX_MSR_BITMAP: 0x%016lx ", value64);
/* Initialize the MSR save/store area */
prepare_auto_msr_area (vcpu);
prepare_auto_msr_area(vcpu);
/* Setup initial value for emulated MSRs */
init_emulated_msrs(vcpu);

21
hypervisor/include/arch/x86/asm/vm_config.h
View File

@@ -182,9 +182,24 @@ struct acrn_vm_config {
* SOS can get the vm_configs[] array through hypercall, but SOS may not
* need to parse these members.
*/
uint16_t clos[MAX_VCPUS_PER_VM]; /* Class of Service, effective only if CONFIG_RDT_ENABLED
* is defined on CAT capable platforms
*/
uint16_t num_pclosids; /* This defines the number of elements in the array pointed to by pclosids */
/* pclosids: a pointer to an array of physical CLOSIDs (pCLOSIDs)) that is defined in vm_configurations.c
* by vmconfig,
* applicable only if CONFIG_RDT_ENABLED is defined on CAT capable platforms.
* The number of elements in the array must be equal to the value given by num_pclosids
*/
uint16_t *pclosids;
/* max_type_pcbm (type: l2 or l3) specifies the allocated portion of physical cache
* for the VM and is a contiguous capacity bitmask (CBM) starting at bit position low
* (the lowest assigned physical cache way) and ending at position high
* (the highest assigned physical cache way, inclusive).
* As CBM only allows contiguous '1' combinations, so max_type_pcbm essentially
* is a bitmask that selects/covers all the physical cache ways assigned to the VM.
*/
uint32_t max_l2_pcbm;
uint32_t max_l3_pcbm;
struct vuart_config vuart[MAX_VUART_NUM_PER_VM];/* vuart configuration for VM */