diff --git a/hypervisor/arch/x86/guest/guest.c b/hypervisor/arch/x86/guest/guest.c
index 1cc0a76e9..318afd494 100644
--- a/hypervisor/arch/x86/guest/guest.c
+++ b/hypervisor/arch/x86/guest/guest.c
@@ -82,7 +82,7 @@ inline uint64_t vcpumask2pcpumask(struct vm *vm, uint64_t vdmask)
 	while ((vcpu_id = ffs64(vdmask)) >= 0) {
 		bitmap_clear(vcpu_id, &vdmask);
 		vcpu = vcpu_from_vid(vm, vcpu_id);
-		ASSERT(vcpu, "vcpu_from_vid failed");
+		ASSERT(vcpu != NULL, "vcpu_from_vid failed");
 		bitmap_set(vcpu->pcpu_id, &dmask);
 	}
 
@@ -113,9 +113,9 @@ enum vm_paging_mode get_vcpu_paging_mode(struct vcpu *vcpu)
 	if (cpu_mode == CPU_MODE_REAL)
 		return PAGING_MODE_0_LEVEL;
 	else if (cpu_mode == CPU_MODE_PROTECTED) {
-		if (cur_context->cr4 & CR4_PAE)
+		if ((cur_context->cr4 & CR4_PAE) != 0U)
 			return PAGING_MODE_3_LEVEL;
-		else if (cur_context->cr0 & CR0_PG)
+		else if ((cur_context->cr0 & CR0_PG) != 0U)
 			return PAGING_MODE_2_LEVEL;
 		return PAGING_MODE_0_LEVEL;
 	} else	/* compatibility or 64bit mode */
@@ -157,12 +157,12 @@ static int _gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_info,
 			entry = *((uint64_t *)(base + 8 * index));
 
 		/* check if the entry present */
-		if (!(entry & MMU_32BIT_PDE_P)) {
+		if ((entry & MMU_32BIT_PDE_P) == 0U) {
 			ret = -EFAULT;
 			goto out;
 		}
 		/* check for R/W */
-		if (pw_info->is_write_access && !(entry & MMU_32BIT_PDE_RW)) {
+		if (pw_info->is_write_access && ((entry & MMU_32BIT_PDE_RW) == 0U)) {
 			/* Case1: Supermode and wp is 1
 			 * Case2: Usermode */
 			if (!(!pw_info->is_user_mode && !pw_info->wp))
@@ -171,14 +171,14 @@ static int _gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_info,
 		/* check for nx, since for 32-bit paing, the XD bit is
 		 * reserved(0), use the same logic as PAE/4-level paging */
 		if (pw_info->is_inst_fetch && pw_info->nxe &&
-		    (entry & MMU_MEM_ATTR_BIT_EXECUTE_DISABLE))
+		    ((entry & MMU_MEM_ATTR_BIT_EXECUTE_DISABLE) != 0U))
 			fault = 1;
 
 		/* check for U/S */
-		if (!(entry & MMU_32BIT_PDE_US) && pw_info->is_user_mode)
+		if (((entry & MMU_32BIT_PDE_US) == 0U) && pw_info->is_user_mode)
 			fault = 1;
 
-		if (pw_info->pse && (i > 0 && (entry & MMU_32BIT_PDE_PS)))
+		if (pw_info->pse && (i > 0 && ((entry & MMU_32BIT_PDE_PS) != 0U)))
 			break;
 		addr = entry;
 	}
@@ -190,7 +190,7 @@ static int _gva2gpa_common(struct vcpu *vcpu, struct page_walk_info *pw_info,
 	*gpa = entry | (gva & (page_size - 1));
 out:
 
-	if (fault) {
+	if (fault != 0) {
 		ret = -EFAULT;
 		*err_code |= PAGE_FAULT_P_FLAG;
 	}
@@ -216,7 +216,7 @@ static int _gva2gpa_pae(struct vcpu *vcpu, struct page_walk_info *pw_info,
 	index = (gva >> 30) & 0x3;
 	entry = base[index];
 
-	if (!(entry & MMU_32BIT_PDE_P)) {
+	if ((entry & MMU_32BIT_PDE_P) == 0U) {
 		ret = -EFAULT;
 		goto out;
 	}
@@ -256,7 +256,7 @@ int gva2gpa(struct vcpu *vcpu, uint64_t gva, uint64_t *gpa,
 	struct page_walk_info pw_info;
 	int ret = 0;
 
-	if (!gpa || !err_code)
+	if ((gpa == NULL) || (err_code == NULL))
 		return -EINVAL;
 	*gpa = 0;
 
@@ -306,7 +306,7 @@ static inline int32_t _copy_gpa(struct vm *vm, void *h_ptr, uint64_t gpa,
 		return -EINVAL;
 	}
 
-	if (fix_pg_size)
+	if (fix_pg_size != 0)
 		pg_size = fix_pg_size;
 
 	off_in_pg = gpa & (pg_size - 1);
@@ -418,7 +418,7 @@ void init_e820(void)
 		struct multiboot_info *mbi =
 			(struct multiboot_info *)((uint64_t)boot_regs[1]);
 		pr_info("Multiboot info detected\n");
-		if (mbi->mi_flags & 0x40) {
+		if ((mbi->mi_flags & 0x40) != 0U) {
 			struct multiboot_mmap *mmap =
 				(struct multiboot_mmap *)
 				((uint64_t)mbi->mi_mmap_addr);
@@ -447,7 +447,7 @@ void init_e820(void)
 			}
 		}
 	} else
-		ASSERT(0, "no multiboot info found");
+		ASSERT(false, "no multiboot info found");
 }
 
 
diff --git a/hypervisor/arch/x86/guest/instr_emul.c b/hypervisor/arch/x86/guest/instr_emul.c
index abf860458..8c6751ca2 100644
--- a/hypervisor/arch/x86/guest/instr_emul.c
+++ b/hypervisor/arch/x86/guest/instr_emul.c
@@ -271,8 +271,8 @@ vie_calc_bytereg(struct vie *vie, enum vm_reg_name *reg, int *lhbr)
 	 * of the 'ModRM:reg' field address the legacy high-byte registers,
 	 * %ah, %ch, %dh and %bh respectively.
 	 */
-	if (!vie->rex_present) {
-		if (vie->reg & 0x4) {
+	if (vie->rex_present == 0U) {
+		if ((vie->reg & 0x4) != 0U) {
 			*lhbr = 1;
 			*reg = gpr_map[vie->reg & 0x3];
 		}
@@ -293,7 +293,7 @@ vie_read_bytereg(struct vcpu *vcpu, struct vie *vie, uint8_t *rval)
 	 * To obtain the value of a legacy high byte register shift the
 	 * base register right by 8 bits (%ah = %rax >> 8).
 	 */
-	if (lhbr)
+	if (lhbr != 0)
 		*rval = val >> 8;
 	else
 		*rval = val;
@@ -312,7 +312,7 @@ vie_write_bytereg(struct vcpu *vcpu, struct vie *vie, uint8_t byte)
 	if (error == 0) {
 		val = byte;
 		mask = 0xff;
-		if (lhbr) {
+		if (lhbr != 0) {
 			/*
 			 * Shift left by 8 to store 'byte' in a legacy high
 			 * byte register.
@@ -337,7 +337,7 @@ vie_update_register(struct vcpu *vcpu, enum vm_reg_name reg,
 	case 1:
 	case 2:
 		error = vie_read_register(vcpu, reg, &origval);
-		if (error)
+		if (error != 0)
 			return error;
 		val &= size2mask[size];
 		val |= origval & ~size2mask[size];
@@ -540,7 +540,7 @@ emulate_movx(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 
 		/* get the first operand */
 		error = memread(vcpu, gpa, &val, 1, arg);
-		if (error)
+		if (error != 0)
 			break;
 
 		/* get the second operand */
@@ -561,7 +561,7 @@ emulate_movx(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 		 * REX.W + 0F B7/r	movzx r64, r/m16
 		 */
 		error = memread(vcpu, gpa, &val, 2, arg);
-		if (error)
+		if (error != 0)
 			return error;
 
 		reg = gpr_map[vie->reg];
@@ -583,7 +583,7 @@ emulate_movx(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 
 		/* get the first operand */
 		error = memread(vcpu, gpa, &val, 1, arg);
-		if (error)
+		if (error != 0)
 			break;
 
 		/* get the second operand */
@@ -626,7 +626,7 @@ get_gla(struct vcpu *vcpu, __unused struct vie *vie,
 	}
 
 	if (vie_calculate_gla(paging->cpu_mode, seg, &desc, val, opsize,
-	    addrsize, prot, gla)) {
+	    addrsize, prot, gla) != 0) {
 		if (seg == VM_REG_GUEST_SS)
 			/*vm_inject_ss(vcpu, 0);*/
 			pr_err("TODO: inject ss exception");
@@ -636,7 +636,7 @@ get_gla(struct vcpu *vcpu, __unused struct vie *vie,
 		goto guest_fault;
 	}
 
-	if (vie_canonical_check(paging->cpu_mode, *gla)) {
+	if (vie_canonical_check(paging->cpu_mode, *gla) != 0) {
 		if (seg == VM_REG_GUEST_SS)
 			/*vm_inject_ss(vcpu, 0);*/
 			pr_err("TODO: inject ss exception");
@@ -646,7 +646,7 @@ get_gla(struct vcpu *vcpu, __unused struct vie *vie,
 		goto guest_fault;
 	}
 
-	if (vie_alignment_check(paging->cpl, opsize, cr0, rflags, *gla)) {
+	if (vie_alignment_check(paging->cpl, opsize, cr0, rflags, *gla) != 0) {
 		/*vm_inject_ac(vcpu, 0);*/
 		pr_err("TODO: inject ac exception");
 		goto guest_fault;
@@ -683,9 +683,9 @@ emulate_movs(struct vcpu *vcpu, __unused uint64_t gpa, struct vie *vie,
 	 */
 	repeat = vie->repz_present | vie->repnz_present;
 
-	if (repeat) {
+	if (repeat != 0) {
 		error = vie_read_register(vcpu, VM_REG_GUEST_RCX, &rcx);
-		ASSERT(!error, "%s: error %d getting rcx", __func__, error);
+		ASSERT(error == 0, "%s: error %d getting rcx", __func__, error);
 
 		/*
 		 * The count register is %rcx, %ecx or %cx depending on the
@@ -697,16 +697,16 @@ emulate_movs(struct vcpu *vcpu, __unused uint64_t gpa, struct vie *vie,
 		}
 	}
 
-	seg = vie->segment_override ? vie->segment_register : VM_REG_GUEST_DS;
+	seg = (vie->segment_override != 0U) ? vie->segment_register : VM_REG_GUEST_DS;
 	error = get_gla(vcpu, vie, paging, opsize, vie->addrsize,
 	    PROT_READ, seg, VM_REG_GUEST_RSI, &srcaddr, &fault);
-	if (error || fault)
+	if ((error != 0) || (fault != 0))
 		goto done;
 
 	error = get_gla(vcpu, vie, paging, opsize, vie->addrsize,
 		PROT_WRITE, VM_REG_GUEST_ES, VM_REG_GUEST_RDI, &dstaddr,
 		&fault);
-	if (error || fault)
+	if ((error != 0) || (fault != 0))
 		goto done;
 
 	memcpy_s((char *)dstaddr, 16, (char *)srcaddr, opsize);
@@ -720,7 +720,7 @@ emulate_movs(struct vcpu *vcpu, __unused uint64_t gpa, struct vie *vie,
 	error = vie_read_register(vcpu, VM_REG_GUEST_RFLAGS, &rflags);
 	ASSERT(error == 0, "%s: error %d getting rflags", __func__, error);
 
-	if (rflags & PSL_D) {
+	if ((rflags & PSL_D) != 0U) {
 		rsi -= opsize;
 		rdi -= opsize;
 	} else {
@@ -736,11 +736,11 @@ emulate_movs(struct vcpu *vcpu, __unused uint64_t gpa, struct vie *vie,
 			vie->addrsize);
 	ASSERT(error == 0, "%s: error %d updating rdi", __func__, error);
 
-	if (repeat) {
+	if (repeat != 0) {
 		rcx = rcx - 1;
 		error = vie_update_register(vcpu, VM_REG_GUEST_RCX,
 				rcx, vie->addrsize);
-		ASSERT(!error, "%s: error %d updating rcx", __func__, error);
+		ASSERT(error == 0, "%s: error %d updating rcx", __func__, error);
 
 		/*
 		 * Repeat the instruction if the count register is not zero.
@@ -766,9 +766,9 @@ emulate_stos(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 	opsize = (vie->op.op_byte == 0xAA) ? 1 : vie->opsize;
 	repeat = vie->repz_present | vie->repnz_present;
 
-	if (repeat) {
+	if (repeat != 0) {
 		error = vie_read_register(vcpu, VM_REG_GUEST_RCX, &rcx);
-		ASSERT(!error, "%s: error %d getting rcx", __func__, error);
+		ASSERT(error == 0, "%s: error %d getting rcx", __func__, error);
 
 		/*
 		 * The count register is %rcx, %ecx or %cx depending on the
@@ -779,10 +779,10 @@ emulate_stos(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 	}
 
 	error = vie_read_register(vcpu, VM_REG_GUEST_RAX, &val);
-	ASSERT(!error, "%s: error %d getting rax", __func__, error);
+	ASSERT(error == 0, "%s: error %d getting rax", __func__, error);
 
 	error = memwrite(vcpu, gpa, val, opsize, arg);
-	if (error)
+	if (error != 0)
 		return error;
 
 	error = vie_read_register(vcpu, VM_REG_GUEST_RDI, &rdi);
@@ -791,7 +791,7 @@ emulate_stos(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 	error = vie_read_register(vcpu, VM_REG_GUEST_RFLAGS, &rflags);
 	ASSERT(error == 0, "%s: error %d getting rflags", __func__, error);
 
-	if (rflags & PSL_D)
+	if ((rflags & PSL_D) != 0U)
 		rdi -= opsize;
 	else
 		rdi += opsize;
@@ -800,11 +800,11 @@ emulate_stos(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 			vie->addrsize);
 	ASSERT(error == 0, "%s: error %d updating rdi", __func__, error);
 
-	if (repeat) {
+	if (repeat != 0) {
 		rcx = rcx - 1;
 		error = vie_update_register(vcpu, VM_REG_GUEST_RCX,
 				rcx, vie->addrsize);
-		ASSERT(!error, "%s: error %d updating rcx", __func__, error);
+		ASSERT(error == 0, "%s: error %d updating rcx", __func__, error);
 
 		/*
 		 * Repeat the instruction if the count register is not zero.
@@ -849,12 +849,12 @@ emulate_test(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 		/* get the first operand */
 		reg = gpr_map[vie->reg];
 		error = vie_read_register(vcpu, reg, &val1);
-		if (error)
+		if (error != 0)
 			break;
 
 		/* get the second operand */
 		error = memread(vcpu, gpa, &val2, size, arg);
-		if (error)
+		if (error != 0)
 			break;
 
 		/* perform the operation and write the result */
@@ -863,11 +863,11 @@ emulate_test(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 	default:
 		break;
 	}
-	if (error)
+	if (error != 0)
 		return error;
 
 	error = vie_read_register(vcpu, VM_REG_GUEST_RFLAGS, &rflags);
-	if (error)
+	if (error != 0)
 		return error;
 
 	/*
@@ -910,12 +910,12 @@ emulate_and(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 		/* get the first operand */
 		reg = gpr_map[vie->reg];
 		error = vie_read_register(vcpu, reg, &val1);
-		if (error)
+		if (error != 0)
 			break;
 
 		/* get the second operand */
 		error = memread(vcpu, gpa, &val2, size, arg);
-		if (error)
+		if (error != 0)
 			break;
 
 		/* perform the operation and write the result */
@@ -940,7 +940,7 @@ emulate_and(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 
 		/* get the first operand */
 		error = memread(vcpu, gpa, &val1, size, arg);
-		if (error)
+		if (error != 0)
 			break;
 
 		/*
@@ -953,11 +953,11 @@ emulate_and(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 	default:
 		break;
 	}
-	if (error)
+	if (error != 0)
 		return error;
 
 	error = vie_read_register(vcpu, VM_REG_GUEST_RFLAGS, &rflags);
-	if (error)
+	if (error != 0)
 		return error;
 
 	/*
@@ -1008,7 +1008,7 @@ emulate_or(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 
 		/* get the first operand */
 		error = memread(vcpu, gpa, &val1, size, arg);
-		if (error)
+		if (error != 0)
 			break;
 
 		/*
@@ -1028,13 +1028,13 @@ emulate_or(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 
 		/* get the first operand */
 		error = memread(vcpu, gpa, &val1, size, arg);
-		if (error)
+		if (error != 0)
 			break;
 
 		/* get the second operand */
 		reg = gpr_map[vie->reg];
 		error = vie_read_register(vcpu, reg, &val2);
-		if (error)
+		if (error != 0)
 			break;
 
 		/* perform the operation and write the result */
@@ -1046,11 +1046,11 @@ emulate_or(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 	default:
 		break;
 	}
-	if (error)
+	if (error != 0)
 		return error;
 
 	error = vie_read_register(vcpu, VM_REG_GUEST_RFLAGS, &rflags);
-	if (error)
+	if (error != 0)
 		return error;
 
 	/*
@@ -1098,12 +1098,12 @@ emulate_cmp(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 		/* Get the register operand */
 		reg = gpr_map[vie->reg];
 		error = vie_read_register(vcpu, reg, &regop);
-		if (error)
+		if (error != 0)
 			return error;
 
 		/* Get the memory operand */
 		error = memread(vcpu, gpa, &memop, size, arg);
-		if (error)
+		if (error != 0)
 			return error;
 
 		if (vie->op.op_byte == 0x3B) {
@@ -1146,7 +1146,7 @@ emulate_cmp(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 
 		/* get the first operand */
 		error = memread(vcpu, gpa, &op1, size, arg);
-		if (error)
+		if (error != 0)
 			return error;
 
 		rflags2 = getcc(size, op1, vie->immediate);
@@ -1155,7 +1155,7 @@ emulate_cmp(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 		return -EINVAL;
 	}
 	error = vie_read_register(vcpu, VM_REG_GUEST_RFLAGS, &rflags);
-	if (error)
+	if (error != 0)
 		return error;
 	rflags &= ~RFLAGS_STATUS_BITS;
 	rflags |= rflags2 & RFLAGS_STATUS_BITS;
@@ -1189,12 +1189,12 @@ emulate_sub(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 		/* get the first operand */
 		reg = gpr_map[vie->reg];
 		error = vie_read_register(vcpu, reg, &val1);
-		if (error)
+		if (error != 0)
 			break;
 
 		/* get the second operand */
 		error = memread(vcpu, gpa, &val2, size, arg);
-		if (error)
+		if (error != 0)
 			break;
 
 		/* perform the operation and write the result */
@@ -1206,11 +1206,11 @@ emulate_sub(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 		break;
 	}
 
-	if (!error) {
+	if (error == 0) {
 		rflags2 = getcc(size, val1, val2);
 		error = vie_read_register(vcpu, VM_REG_GUEST_RFLAGS,
 				&rflags);
-		if (error)
+		if (error != 0)
 			return error;
 
 		rflags &= ~RFLAGS_STATUS_BITS;
@@ -1252,7 +1252,7 @@ emulate_stack_op(struct vcpu *vcpu, uint64_t mmio_gpa, struct vie *vie,
 		 *   override prefix (66H).
 		 */
 		stackaddrsize = 8;
-		size = vie->opsize_override ? 2 : 8;
+		size = (vie->opsize_override != 0U) ? 2 : 8;
 	} else {
 		/*
 		 * In protected or compatibility mode the 'B' flag in the
@@ -1262,7 +1262,7 @@ emulate_stack_op(struct vcpu *vcpu, uint64_t mmio_gpa, struct vie *vie,
 		error = vm_get_seg_desc(vcpu, VM_REG_GUEST_SS, &ss_desc);
 		ASSERT(error == 0, "%s: error %d getting SS descriptor",
 					__func__, error);
-		if (SEG_DESC_DEF32(ss_desc.access))
+		if ((_Bool)SEG_DESC_DEF32(ss_desc.access))
 			stackaddrsize = 4;
 		else
 			stackaddrsize = 2;
@@ -1276,22 +1276,22 @@ emulate_stack_op(struct vcpu *vcpu, uint64_t mmio_gpa, struct vie *vie,
 
 	error = vie_read_register(vcpu, VM_REG_GUEST_RSP, &rsp);
 	ASSERT(error == 0, "%s: error %d getting rsp", __func__, error);
-	if (pushop)
+	if (pushop != 0)
 		rsp -= size;
 
 	if (vie_calculate_gla(paging->cpu_mode, VM_REG_GUEST_SS, &ss_desc,
-	    rsp, size, stackaddrsize, pushop ? PROT_WRITE : PROT_READ,
-	    &stack_gla)) {
+	    rsp, size, stackaddrsize, (pushop != 0)? PROT_WRITE : PROT_READ,
+	    &stack_gla) != 0) {
 		/*vm_inject_ss(vcpu, 0);*/
 		pr_err("TODO: inject ss exception");
 	}
 
-	if (vie_canonical_check(paging->cpu_mode, stack_gla)) {
+	if (vie_canonical_check(paging->cpu_mode, stack_gla) != 0) {
 		/*vm_inject_ss(vcpu, 0);*/
 		pr_err("TODO: inject ss exception");
 	}
 
-	if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla)) {
+	if (vie_alignment_check(paging->cpl, size, cr0, rflags, stack_gla) != 0) {
 		/*vm_inject_ac(vcpu, 0);*/
 		pr_err("TODO: inject ac exception");
 		return 0;
@@ -1302,7 +1302,7 @@ emulate_stack_op(struct vcpu *vcpu, uint64_t mmio_gpa, struct vie *vie,
 	 * take care of data trans if stack_gpa be used for memwrite in
 	 * the future.
 	 */
-	if (pushop)
+	if (pushop != 0)
 		err_code |= PAGE_FAULT_WR_FLAG;
 	error = gva2gpa(vcpu, stack_gla, &stack_gpa, &err_code);
 	if (error == -EFAULT) {
@@ -1310,7 +1310,7 @@ emulate_stack_op(struct vcpu *vcpu, uint64_t mmio_gpa, struct vie *vie,
 		return error;
 	} else if (error < 0)
 		return error;
-	if (pushop) {
+	if (pushop != 0) {
 		error = memread(vcpu, mmio_gpa, &val, size, arg);
 		if (error == 0)
 			error = memwrite(vcpu, stack_gpa, val, size, arg);
@@ -1422,7 +1422,7 @@ emulate_bittest(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 	ASSERT(error == 0, "%s: error %d getting rflags", __func__, error);
 
 	error = memread(vcpu, gpa, &val, vie->opsize, memarg);
-	if (error)
+	if (error != 0)
 		return error;
 
 	/*
@@ -1433,7 +1433,7 @@ emulate_bittest(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 	bitoff = vie->immediate & bitmask;
 
 	/* Copy the bit into the Carry flag in %rflags */
-	if (val & (1UL << bitoff))
+	if ((val & (1UL << bitoff)) != 0U)
 		rflags |= PSL_C;
 	else
 		rflags &= ~PSL_C;
@@ -1451,7 +1451,7 @@ vmm_emulate_instruction(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
 {
 	int error;
 
-	if (!vie->decoded)
+	if (vie->decoded == 0U)
 		return -EINVAL;
 	switch (vie->op.op_type) {
 	case VIE_OP_TYPE_GROUP1:
@@ -1524,7 +1524,7 @@ vie_alignment_check(int cpl, int size, uint64_t cr0, uint64_t rf, uint64_t gla)
 	if (cpl != 3 || (cr0 & CR0_AM) == 0 || (rf & PSL_AC) == 0)
 		return 0;
 
-	return (gla & (size - 1)) ? 1 : 0;
+	return ((gla & (size - 1)) != 0U) ? 1 : 0;
 }
 
 int
@@ -1540,7 +1540,7 @@ vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla)
 	 * most significant 16 bits.
 	 */
 	mask = ~((1UL << 48) - 1);
-	if (gla & (1UL << 47))
+	if ((gla & (1UL << 47)) != 0U)
 		return (gla & mask) != mask;
 	else
 		return (gla & mask) != 0;
@@ -1585,7 +1585,7 @@ vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
 		 * then the descriptor is unusable and attempting to use
 		 * it results in a #GP(0).
 		 */
-		if (SEG_DESC_UNUSABLE(desc->access))
+		if ((_Bool)SEG_DESC_UNUSABLE(desc->access))
 			return -1;
 
 		/*
@@ -1594,7 +1594,7 @@ vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
 		 * descriptor that is not present. If this was the case then
 		 * it would have been checked before the VM-exit.
 		 */
-		ASSERT(SEG_DESC_PRESENT(desc->access),
+		ASSERT((_Bool)SEG_DESC_PRESENT(desc->access),
 		    "segment %d not present: %#x", seg, desc->access);
 
 		/*
@@ -1605,18 +1605,18 @@ vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
 			"segment %d has invalid descriptor type %#x",
 			seg, type);
 
-		if (prot & PROT_READ) {
+		if ((prot & PROT_READ) != 0) {
 			/* #GP on a read access to a exec-only code segment */
 			if ((type & 0xA) == 0x8)
 				return -1;
 		}
 
-		if (prot & PROT_WRITE) {
+		if ((prot & PROT_WRITE) != 0) {
 			/*
 			 * #GP on a write access to a code segment or a
 			 * read-only data segment.
 			 */
-			if (type & 0x8)			/* code segment */
+			if ((type & 0x8) != 0)		/* code segment */
 				return -1;
 
 			if ((type & 0xA) == 0)		/* read-only data seg */
@@ -1684,7 +1684,7 @@ vie_init(struct vie *vie, struct vcpu *vcpu)
 	vie->index_register = VM_REG_LAST;
 	vie->segment_register = VM_REG_LAST;
 
-	if (inst_len) {
+	if (inst_len != 0U) {
 		int ret;
 		uint64_t guest_rip_gva =
 		vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].rip;
@@ -1757,7 +1757,7 @@ decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
 	uint8_t x;
 
 	while (1) {
-		if (vie_peek(vie, &x))
+		if (vie_peek(vie, &x) != 0)
 			return -1;
 
 		if (x == 0x66)
@@ -1786,10 +1786,10 @@ decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
 	 */
 	if (cpu_mode == CPU_MODE_64BIT && x >= 0x40 && x <= 0x4F) {
 		vie->rex_present = 1;
-		vie->rex_w = x & 0x8 ? 1 : 0;
-		vie->rex_r = x & 0x4 ? 1 : 0;
-		vie->rex_x = x & 0x2 ? 1 : 0;
-		vie->rex_b = x & 0x1 ? 1 : 0;
+		vie->rex_w = (x & 0x8) != 0U ? 1 : 0;
+		vie->rex_r = (x & 0x4) != 0U ? 1 : 0;
+		vie->rex_x = (x & 0x2) != 0U ? 1 : 0;
+		vie->rex_b = (x & 0x1) != 0U ? 1 : 0;
 		vie_advance(vie);
 	}
 
@@ -1801,21 +1801,21 @@ decode_prefixes(struct vie *vie, enum vm_cpu_mode cpu_mode, int cs_d)
 		 * Default address size is 64-bits and default operand size
 		 * is 32-bits.
 		 */
-		vie->addrsize = vie->addrsize_override ? 4 : 8;
-		if (vie->rex_w)
+		vie->addrsize = (vie->addrsize_override != 0U)? 4 : 8;
+		if (vie->rex_w != 0U)
 			vie->opsize = 8;
-		else if (vie->opsize_override)
+		else if (vie->opsize_override != 0U)
 			vie->opsize = 2;
 		else
 			vie->opsize = 4;
-	} else if (cs_d) {
+	} else if (cs_d != 0) {
 		/* Default address and operand sizes are 32-bits */
-		vie->addrsize = vie->addrsize_override ? 2 : 4;
-		vie->opsize = vie->opsize_override ? 2 : 4;
+		vie->addrsize = vie->addrsize_override != 0U ? 2 : 4;
+		vie->opsize = vie->opsize_override != 0U ? 2 : 4;
 	} else {
 		/* Default address and operand sizes are 16-bits */
-		vie->addrsize = vie->addrsize_override ? 4 : 2;
-		vie->opsize = vie->opsize_override ? 4 : 2;
+		vie->addrsize = vie->addrsize_override != 0U ? 4 : 2;
+		vie->opsize = vie->opsize_override != 0U ? 4 : 2;
 	}
 	return 0;
 }
@@ -1825,7 +1825,7 @@ decode_two_byte_opcode(struct vie *vie)
 {
 	uint8_t x;
 
-	if (vie_peek(vie, &x))
+	if (vie_peek(vie, &x) != 0)
 		return -1;
 
 	vie->op = two_byte_opcodes[x];
@@ -1842,7 +1842,7 @@ decode_opcode(struct vie *vie)
 {
 	uint8_t x;
 
-	if (vie_peek(vie, &x))
+	if (vie_peek(vie, &x) != 0)
 		return -1;
 
 	vie->op = one_byte_opcodes[x];
@@ -1863,13 +1863,13 @@ decode_modrm(struct vie *vie, enum vm_cpu_mode cpu_mode)
 {
 	uint8_t x;
 
-	if (vie->op.op_flags & VIE_OP_F_NO_MODRM)
+	if ((vie->op.op_flags & VIE_OP_F_NO_MODRM) != 0U)
 		return 0;
 
 	if (cpu_mode == CPU_MODE_REAL)
 		return -1;
 
-	if (vie_peek(vie, &x))
+	if (vie_peek(vie, &x) != 0)
 		return -1;
 
 	vie->mod = (x >> 6) & 0x3;
@@ -1950,7 +1950,7 @@ decode_sib(struct vie *vie)
 	if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
 		return 0;
 
-	if (vie_peek(vie, &x))
+	if (vie_peek(vie, &x) != 0)
 		return -1;
 
 	/* De-construct the SIB byte */
@@ -2025,7 +2025,7 @@ decode_displacement(struct vie *vie)
 		panic("decode_displacement: invalid disp_bytes %d", n);
 
 	for (i = 0; i < n; i++) {
-		if (vie_peek(vie, &x))
+		if (vie_peek(vie, &x) != 0)
 			return -1;
 
 		u.buf[i] = x;
@@ -2053,7 +2053,7 @@ decode_immediate(struct vie *vie)
 	} u;
 
 	/* Figure out immediate operand size (if any) */
-	if (vie->op.op_flags & VIE_OP_F_IMM) {
+	if ((vie->op.op_flags & VIE_OP_F_IMM) != 0U) {
 		/*
 		 * Section 2.2.1.5 "Immediates", Intel SDM:
 		 * In 64-bit mode the typical size of immediate operands
@@ -2065,7 +2065,7 @@ decode_immediate(struct vie *vie)
 			vie->imm_bytes = 4;
 		else
 			vie->imm_bytes = 2;
-	} else if (vie->op.op_flags & VIE_OP_F_IMM8) {
+	} else if ((vie->op.op_flags & VIE_OP_F_IMM8) != 0U) {
 		vie->imm_bytes = 1;
 	}
 
@@ -2077,7 +2077,7 @@ decode_immediate(struct vie *vie)
 		"%s: invalid number of immediate bytes: %d", __func__, n);
 
 	for (i = 0; i < n; i++) {
-		if (vie_peek(vie, &x))
+		if (vie_peek(vie, &x) != 0)
 			return -1;
 
 		u.buf[i] = x;
@@ -2117,7 +2117,7 @@ decode_moffset(struct vie *vie)
 
 	u.u64 = 0;
 	for (i = 0; i < n; i++) {
-		if (vie_peek(vie, &x))
+		if (vie_peek(vie, &x) != 0)
 			return -1;
 
 		u.buf[i] = x;
@@ -2130,25 +2130,25 @@ decode_moffset(struct vie *vie)
 int
 __decode_instruction(enum vm_cpu_mode cpu_mode, int cs_d, struct vie *vie)
 {
-	if (decode_prefixes(vie, cpu_mode, cs_d))
+	if (decode_prefixes(vie, cpu_mode, cs_d) != 0)
 		return -1;
 
-	if (decode_opcode(vie))
+	if (decode_opcode(vie) != 0)
 		return -1;
 
-	if (decode_modrm(vie, cpu_mode))
+	if (decode_modrm(vie, cpu_mode) != 0)
 		return -1;
 
-	if (decode_sib(vie))
+	if (decode_sib(vie) != 0)
 		return -1;
 
-	if (decode_displacement(vie))
+	if (decode_displacement(vie) != 0)
 		return -1;
 
-	if (decode_immediate(vie))
+	if (decode_immediate(vie) != 0)
 		return -1;
 
-	if (decode_moffset(vie))
+	if (decode_moffset(vie) != 0)
 		return -1;
 
 	vie->decoded = 1;	/* success */
diff --git a/hypervisor/arch/x86/guest/instr_emul_wrapper.c b/hypervisor/arch/x86/guest/instr_emul_wrapper.c
index 25e076fe3..7f9ac027c 100644
--- a/hypervisor/arch/x86/guest/instr_emul_wrapper.c
+++ b/hypervisor/arch/x86/guest/instr_emul_wrapper.c
@@ -25,7 +25,7 @@ int vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval)
 {
 	struct run_context *cur_context;
 
-	if (!vcpu)
+	if (vcpu == NULL)
 		return -EINVAL;
 	if ((reg >= VM_REG_LAST) || (reg < VM_REG_GUEST_RAX))
 		return -EINVAL;
@@ -50,7 +50,7 @@ int vm_set_register(struct vcpu *vcpu, int reg, uint64_t val)
 {
 	struct run_context *cur_context;
 
-	if (!vcpu)
+	if (vcpu == NULL)
 		return -EINVAL;
 	if ((reg >= VM_REG_LAST) || (reg < VM_REG_GUEST_RAX))
 		return -EINVAL;
@@ -76,7 +76,7 @@ int vm_set_seg_desc(struct vcpu *vcpu, int seg, struct seg_desc *ret_desc)
 	int error;
 	uint32_t base, limit, access;
 
-	if ((!vcpu) || (!ret_desc))
+	if ((vcpu == NULL) || (ret_desc == NULL))
 		return -EINVAL;
 
 	if (!is_segment_register(seg) && !is_descriptor_table(seg))
@@ -98,7 +98,7 @@ int vm_get_seg_desc(struct vcpu *vcpu, int seg, struct seg_desc *desc)
 	int error;
 	uint32_t base, limit, access;
 
-	if ((!vcpu) || (!desc))
+	if ((vcpu == NULL) || (desc == NULL))
 		return -EINVAL;
 
 	if (!is_segment_register(seg) && !is_descriptor_table(seg))
@@ -270,7 +270,7 @@ static void get_guest_paging_info(struct vcpu *vcpu, struct emul_cnx *emul_cnx)
 static int mmio_read(struct vcpu *vcpu, __unused uint64_t gpa, uint64_t *rval,
 		__unused int size, __unused void *arg)
 {
-	if (!vcpu)
+	if (vcpu == NULL)
 		return -EINVAL;
 
 	*rval = vcpu->mmio.value;
@@ -280,7 +280,7 @@ static int mmio_read(struct vcpu *vcpu, __unused uint64_t gpa, uint64_t *rval,
 static int mmio_write(struct vcpu *vcpu, __unused uint64_t gpa, uint64_t wval,
 		__unused int size, __unused void *arg)
 {
-	if (!vcpu)
+	if (vcpu == NULL)
 		return -EINVAL;
 
 	vcpu->mmio.value = wval;
diff --git a/hypervisor/arch/x86/guest/pm.c b/hypervisor/arch/x86/guest/pm.c
index 8dd4bbe32..fb5c0a93a 100644
--- a/hypervisor/arch/x86/guest/pm.c
+++ b/hypervisor/arch/x86/guest/pm.c
@@ -18,7 +18,7 @@ int validate_pstate(struct vm *vm, uint64_t perf_ctl)
 	px_cnt = vm->pm.px_cnt;
 	px_data = vm->pm.px_data;
 
-	if (!px_cnt || !px_data) {
+	if (px_cnt == 0 || px_data == NULL) {
 		return -1;
 	}
 
@@ -38,8 +38,8 @@ static void vm_setup_cpu_px(struct vm *vm)
 	vm->pm.px_cnt = 0;
 	memset(vm->pm.px_data, 0, MAX_PSTATE * sizeof(struct cpu_px_data));
 
-	if ((!boot_cpu_data.state_info.px_cnt)
-		|| (!boot_cpu_data.state_info.px_data)) {
+	if ((boot_cpu_data.state_info.px_cnt == 0)
+		|| (boot_cpu_data.state_info.px_data == NULL)) {
 		return;
 	}
 
@@ -62,8 +62,8 @@ static void vm_setup_cpu_cx(struct vm *vm)
 	vm->pm.cx_cnt = 0;
 	memset(vm->pm.cx_data, 0, MAX_CSTATE * sizeof(struct cpu_cx_data));
 
-	if ((!boot_cpu_data.state_info.cx_cnt)
-		|| (!boot_cpu_data.state_info.cx_data)) {
+	if ((boot_cpu_data.state_info.cx_cnt == 0)
+		|| (boot_cpu_data.state_info.cx_data == NULL)) {
 		return;
 	}
 
diff --git a/hypervisor/arch/x86/guest/ucode.c b/hypervisor/arch/x86/guest/ucode.c
index 1b1e91d6f..22407d124 100644
--- a/hypervisor/arch/x86/guest/ucode.c
+++ b/hypervisor/arch/x86/guest/ucode.c
@@ -24,7 +24,7 @@ uint64_t get_microcode_version(void)
  * header is zero, the ucode length is 2000
  */
 #define	UCODE_GET_DATA_SIZE(uhdr)	\
-	(uhdr.data_size ? uhdr.data_size : 2000)
+	((uhdr.data_size != 0U) ? uhdr.data_size : 2000)
 void acrn_update_ucode(struct vcpu *vcpu, uint64_t v)
 {
 	uint64_t gva;
diff --git a/hypervisor/arch/x86/guest/vioapic.c b/hypervisor/arch/x86/guest/vioapic.c
index b86f45008..395578154 100644
--- a/hypervisor/arch/x86/guest/vioapic.c
+++ b/hypervisor/arch/x86/guest/vioapic.c
@@ -86,7 +86,7 @@ vioapic_send_intr(struct vioapic *vioapic, int pin)
 
 	phys = ((low & IOAPIC_RTE_DESTMOD) == IOAPIC_RTE_DESTPHY);
 	delmode = low & IOAPIC_RTE_DELMOD;
-	level = low & IOAPIC_RTE_TRGRLVL ? true : false;
+	level = (low & IOAPIC_RTE_TRGRLVL) != 0U ? true : false;
 	if (level)
 		vioapic->rtbl[pin].reg |= IOAPIC_RTE_REM_IRR;
 
@@ -204,7 +204,7 @@ vioapic_update_tmr(struct vcpu *vcpu)
 	for (pin = 0; pin < vioapic_pincount(vioapic->vm); pin++) {
 		low = vioapic->rtbl[pin].reg;
 
-		level = low & IOAPIC_RTE_TRGRLVL ? true : false;
+		level = (low & IOAPIC_RTE_TRGRLVL) != 0U ? true : false;
 
 		/*
 		 * For a level-triggered 'pin' let the vlapic figure out if
@@ -240,9 +240,9 @@ vioapic_read(struct vioapic *vioapic, uint32_t addr)
 
 	/* redirection table entries */
 	if (regnum >= IOAPIC_REDTBL &&
-	    regnum < IOAPIC_REDTBL + vioapic_pincount(vioapic->vm) * 2) {
+	    (regnum < IOAPIC_REDTBL + vioapic_pincount(vioapic->vm) * 2) != 0) {
 		pin = (regnum - IOAPIC_REDTBL) / 2;
-		if ((regnum - IOAPIC_REDTBL) % 2)
+		if (((regnum - IOAPIC_REDTBL) % 2) != 0)
 			rshift = 32;
 		else
 			rshift = 0;
@@ -307,9 +307,9 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
 
 	/* redirection table entries */
 	if (regnum >= IOAPIC_REDTBL &&
-	    regnum < IOAPIC_REDTBL + vioapic_pincount(vioapic->vm) * 2) {
+	    (regnum < IOAPIC_REDTBL + vioapic_pincount(vioapic->vm) * 2) != 0) {
 		pin = (regnum - IOAPIC_REDTBL) / 2;
-		if ((regnum - IOAPIC_REDTBL) % 2)
+		if (((regnum - IOAPIC_REDTBL) % 2) != 0)
 			lshift = 32;
 		else
 			lshift = 0;
@@ -323,9 +323,9 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
 
 		changed = last ^ new;
 		/* pin0 from vpic mask/unmask */
-		if (pin == 0 && (changed & IOAPIC_RTE_INTMASK)) {
+		if (pin == 0 && (changed & IOAPIC_RTE_INTMASK) != 0U) {
 			/* mask -> umask */
-			if ((last & IOAPIC_RTE_INTMASK) &&
+			if ((last & IOAPIC_RTE_INTMASK) != 0U &&
 				((new & IOAPIC_RTE_INTMASK) == 0)) {
 				if ((vioapic->vm->vpic_wire_mode ==
 						VPIC_WIRE_NULL) ||
@@ -341,7 +341,7 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
 				}
 			/* unmask -> mask */
 			} else if (((last & IOAPIC_RTE_INTMASK) == 0) &&
-				(new & IOAPIC_RTE_INTMASK)) {
+				(new & IOAPIC_RTE_INTMASK) != 0U) {
 				if (vioapic->vm->vpic_wire_mode ==
 						VPIC_WIRE_IOAPIC) {
 					vioapic->vm->vpic_wire_mode =
@@ -359,7 +359,7 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
 		 * or polarity) have changed then rendezvous all the vcpus
 		 * to update their vlapic trigger-mode registers.
 		 */
-		if (changed & ~(IOAPIC_RTE_INTMASK | IOAPIC_RTE_INTPOL)) {
+		if ((changed & ~(IOAPIC_RTE_INTMASK | IOAPIC_RTE_INTPOL)) != 0U) {
 			int i;
 			struct vcpu *vcpu;
 
@@ -599,7 +599,7 @@ bool vioapic_get_rte(struct vm *vm, int pin, void *rte)
 	struct vioapic *vioapic;
 
 	vioapic = vm_ioapic(vm);
-	if (vioapic && rte) {
+	if ((vioapic != NULL) && (rte != NULL)) {
 		*(uint64_t *)rte = vioapic->rtbl[pin].reg;
 		return true;
 	} else
@@ -614,7 +614,7 @@ void get_vioapic_info(char *str, int str_max, int vmid)
 	bool level, phys, remote_irr, mask;
 	struct vm *vm = get_vm_from_vmid(vmid);
 
-	if (!vm) {
+	if (vm == NULL) {
 		len = snprintf(str, size,
 			"\r\nvm is not exist for vmid %d", vmid);
 		size -= len;
@@ -636,7 +636,7 @@ void get_vioapic_info(char *str, int str_max, int vmid)
 		remote_irr = ((low & IOAPIC_RTE_REM_IRR) == IOAPIC_RTE_REM_IRR);
 		phys = ((low & IOAPIC_RTE_DESTMOD) == IOAPIC_RTE_DESTPHY);
 		delmode = low & IOAPIC_RTE_DELMOD;
-		level = low & IOAPIC_RTE_TRGRLVL ? true : false;
+		level = ((low & IOAPIC_RTE_TRGRLVL) != 0U) ? true : false;
 		vector = low & IOAPIC_RTE_INTVEC;
 		dest = high >> APIC_ID_SHIFT;
 
diff --git a/hypervisor/arch/x86/guest/vlapic.c b/hypervisor/arch/x86/guest/vlapic.c
index f8297089d..071ed0738 100644
--- a/hypervisor/arch/x86/guest/vlapic.c
+++ b/hypervisor/arch/x86/guest/vlapic.c
@@ -446,7 +446,7 @@ vlapic_set_intr_ready(struct vlapic *vlapic, uint32_t vector, bool level)
 		"invalid vector %d", vector);
 
 	lapic = vlapic->apic_page;
-	if (!(lapic->svr & APIC_SVR_ENABLE)) {
+	if ((lapic->svr & APIC_SVR_ENABLE) == 0U) {
 		dev_dbg(ACRN_DBG_LAPIC,
 			"vlapic is software disabled, ignoring interrupt %d",
 			vector);
@@ -460,7 +460,7 @@ vlapic_set_intr_ready(struct vlapic *vlapic, uint32_t vector, bool level)
 		return 1;
 	}
 
-	if (vlapic->ops.apicv_set_intr_ready)
+	if (vlapic->ops.apicv_set_intr_ready != NULL)
 		return (*vlapic->ops.apicv_set_intr_ready)
 			(vlapic, vector, level);
 
@@ -568,7 +568,7 @@ vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset)
 	val = *lvtptr;
 	idx = lvt_off_to_idx(offset);
 
-	if (!(lapic->svr & APIC_SVR_ENABLE))
+	if ((lapic->svr & APIC_SVR_ENABLE) == 0U)
 		val |= APIC_LVT_M;
 	mask = APIC_LVT_M | APIC_LVT_DS | APIC_LVT_VECTOR;
 	switch (offset) {
@@ -593,7 +593,7 @@ vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset)
 		uint32_t last = vlapic_get_lvt(vlapic, offset);
 
 		/* mask -> unmask: may from every vlapic in the vm */
-		if ((last & APIC_LVT_M) && ((val & APIC_LVT_M) == 0)) {
+		if (((last & APIC_LVT_M) != 0U) && ((val & APIC_LVT_M) == 0)) {
 			if (vlapic->vm->vpic_wire_mode == VPIC_WIRE_INTR ||
 				vlapic->vm->vpic_wire_mode == VPIC_WIRE_NULL) {
 				vlapic->vm->vpic_wire_mode = VPIC_WIRE_LAPIC;
@@ -604,7 +604,7 @@ vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset)
 				return;
 			}
 		/* unmask -> mask: only from the vlapic LINT0-ExtINT enabled */
-		} else if (((last & APIC_LVT_M) == 0) && (val & APIC_LVT_M)) {
+		} else if (((last & APIC_LVT_M) == 0) && ((val & APIC_LVT_M) != 0U)) {
 			if (vlapic->vm->vpic_wire_mode == VPIC_WIRE_LAPIC) {
 				vlapic->vm->vpic_wire_mode = VPIC_WIRE_NULL;
 				dev_dbg(ACRN_DBG_LAPIC,
@@ -650,7 +650,7 @@ vlapic_fire_lvt(struct vlapic *vlapic, uint32_t lvt)
 {
 	uint32_t vec, mode;
 
-	if (lvt & APIC_LVT_M)
+	if ((lvt & APIC_LVT_M) != 0U)
 		return 0;
 
 	vec = lvt & APIC_LVT_VECTOR;
@@ -662,7 +662,7 @@ vlapic_fire_lvt(struct vlapic *vlapic, uint32_t lvt)
 			vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR);
 			return 0;
 		}
-		if (vlapic_set_intr_ready(vlapic, vec, false))
+		if (vlapic_set_intr_ready(vlapic, vec, false) != 0)
 			vcpu_make_request(vlapic->vcpu, ACRN_REQUEST_EVENT);
 		break;
 	case APIC_LVT_DM_NMI:
@@ -740,7 +740,7 @@ vlapic_update_ppr(struct vlapic *vlapic)
 		isrptr = &vlapic->apic_page->isr[0];
 		for (vector = 0; vector < 256; vector++) {
 			idx = vector / 32;
-			if (isrptr[idx].val & (1 << (vector % 32))) {
+			if ((isrptr[idx].val & (1 << (vector % 32))) != 0U) {
 				if ((i > vlapic->isrvec_stk_top) ||
 					((i < ISRVEC_STK_SIZE) &&
 					(vlapic->isrvec_stk[i] != vector))) {
@@ -800,7 +800,7 @@ vlapic_set_error(struct vlapic *vlapic, uint32_t mask)
 	uint32_t lvt;
 
 	vlapic->esr_pending |= mask;
-	if (vlapic->esr_firing)
+	if (vlapic->esr_firing != 0)
 		return;
 	vlapic->esr_firing = 1;
 
@@ -998,7 +998,7 @@ vlapic_set_cr8(struct vlapic *vlapic, uint64_t val)
 {
 	uint8_t tpr;
 
-	if (val & ~0xf) {
+	if ((val & ~0xf) != 0U) {
 		vcpu_inject_gp(vlapic->vcpu, 0);
 		return;
 	}
@@ -1158,7 +1158,7 @@ vlapic_pending_intr(struct vlapic *vlapic, uint32_t *vecptr)
 	uint32_t val;
 	struct lapic_reg *irrptr;
 
-	if (vlapic->ops.apicv_pending_intr)
+	if (vlapic->ops.apicv_pending_intr != NULL)
 		return (*vlapic->ops.apicv_pending_intr)(vlapic, vecptr);
 
 	irrptr = &lapic->irr[0];
@@ -1186,7 +1186,7 @@ vlapic_intr_accepted(struct vlapic *vlapic, uint32_t vector)
 	struct lapic_reg *irrptr, *isrptr;
 	int idx, stk_top;
 
-	if (vlapic->ops.apicv_intr_accepted) {
+	if (vlapic->ops.apicv_intr_accepted != NULL) {
 		vlapic->ops.apicv_intr_accepted(vlapic, vector);
 		return;
 	}
@@ -1267,7 +1267,7 @@ vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 	struct lapic *lapic = vlapic->apic_page;
 	int i;
 
-	if (!mmio_access) {
+	if (mmio_access == 0) {
 		/*
 		 * XXX Generate GP fault for MSR accesses in xAPIC mode
 		 */
@@ -1419,7 +1419,7 @@ vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 	/*
 	 * XXX Generate GP fault for MSR accesses in xAPIC mode
 	 */
-	if (!mmio_access) {
+	if (mmio_access == 0) {
 		dev_dbg(ACRN_DBG_LAPIC,
 			"x2APIC MSR write of %#lx to offset %#lx in xAPIC mode",
 			data, offset);
@@ -1647,8 +1647,8 @@ vlapic_enabled(struct vlapic *vlapic)
 {
 	struct lapic *lapic = vlapic->apic_page;
 
-	if ((vlapic->msr_apicbase & APICBASE_ENABLED) &&
-			(lapic->svr & APIC_SVR_ENABLE))
+	if (((vlapic->msr_apicbase & APICBASE_ENABLED) != 0U) &&
+			((lapic->svr & APIC_SVR_ENABLE) != 0U))
 		return true;
 	else
 		return false;
@@ -1749,7 +1749,7 @@ vlapic_set_intr(struct vcpu *vcpu, uint32_t vector, bool level)
 		return -EINVAL;
 
 	vlapic = vcpu->arch_vcpu.vlapic;
-	if (vlapic_set_intr_ready(vlapic, vector, level))
+	if (vlapic_set_intr_ready(vlapic, vector, level) != 0)
 		vcpu_make_request(vcpu, ACRN_REQUEST_EVENT);
 	else
 		ret = -ENODEV;
@@ -1776,7 +1776,7 @@ vlapic_set_local_intr(struct vm *vm, int cpu_id, uint32_t vector)
 		bitmap_clear(cpu_id, &dmask);
 		vlapic = vm_lapic_from_vcpu_id(vm, cpu_id);
 		error = vlapic_trigger_lvt(vlapic, vector);
-		if (error)
+		if (error != 0)
 			break;
 	}
 
@@ -1937,7 +1937,7 @@ vlapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size)
 	 * Memory mapped local apic accesses must be 4 bytes wide and
 	 * aligned on a 16-byte boundary.
 	 */
-	if (size != 4 || off & 0xf)
+	if (size != 4 || (off & 0xf) != 0U)
 		return -EINVAL;
 
 	vlapic = vcpu->arch_vcpu.vlapic;
@@ -1961,7 +1961,7 @@ vlapic_mmio_read(struct vcpu *vcpu, uint64_t gpa, uint64_t *rval,
 	 * wide, alas not all OSes follow suggestions.
 	 */
 	off &= ~3;
-	if (off & 0xf)
+	if ((off & 0xf) != 0U)
 		return -EINVAL;
 
 	vlapic = vcpu->arch_vcpu.vlapic;
@@ -2040,7 +2040,7 @@ int vlapic_create(struct vcpu *vcpu)
 				(uint64_t)DEFAULT_APIC_BASE,
 				(uint64_t)DEFAULT_APIC_BASE +
 				CPU_PAGE_SIZE,
-				(void *) 0))
+				(void *) 0) != 0)
 			return -1;
 	}
 
@@ -2112,7 +2112,7 @@ apicv_pending_intr(struct vlapic *vlapic, __unused uint32_t *vecptr)
 	pir_desc = vlapic->pir_desc;
 
 	pending = atomic_load64((long *)&pir_desc->pending);
-	if (!pending)
+	if (pending == 0U)
 		return 0;
 
 	lapic = vlapic->apic_page;
@@ -2290,7 +2290,7 @@ int apic_access_vmexit_handler(struct vcpu *vcpu)
 		return ret;
 
 	if (access_type == 1) {
-		if (!emulate_instruction(vcpu))
+		if (emulate_instruction(vcpu) == 0)
 			vlapic_write(vlapic, 1, offset, vcpu->mmio.value);
 	} else if (access_type == 0) {
 		vlapic_read(vlapic, 1, offset, &vcpu->mmio.value);
diff --git a/hypervisor/arch/x86/guest/vpic.c b/hypervisor/arch/x86/guest/vpic.c
index e5846e50e..574db20a4 100644
--- a/hypervisor/arch/x86/guest/vpic.c
+++ b/hypervisor/arch/x86/guest/vpic.c
@@ -37,8 +37,8 @@
 
 #define vm_pic(vm)	(vm->vpic)
 
-#define true                                          1
-#define false                                         0
+#define true                                          ((_Bool) 1)
+#define false                                         ((_Bool) 0)
 
 #define ACRN_DBG_PIC	6
 
@@ -104,12 +104,12 @@ static inline int vpic_get_highest_isrpin(struct pic *pic)
 	PIC_PIN_FOREACH(pin, pic, i) {
 		bit = (1 << pin);
 
-		if (pic->service & bit) {
+		if ((pic->service & bit) != 0U) {
 			/*
 			 * An IS bit that is masked by an IMR bit will not be
 			 * cleared by a non-specific EOI in Special Mask Mode.
 			 */
-			if (pic->smm && (pic->mask & bit) != 0)
+			if ((pic->smm != 0U) && (pic->mask & bit) != 0)
 				continue;
 			else
 				return pin;
@@ -139,7 +139,7 @@ static inline int vpic_get_highest_irrpin(struct pic *pic)
 	 * other levels that are not masked. In other words the ISR has no
 	 * bearing on the levels that can generate interrupts.
 	 */
-	if (pic->smm)
+	if (pic->smm != 0U)
 		serviced = 0;
 
 	PIC_PIN_FOREACH(pin, pic, tmp) {
@@ -341,7 +341,7 @@ bool vpic_is_pin_mask(struct vpic *vpic, uint8_t virt_pin)
 	} else
 		return true;
 
-	if (pic->mask & (1 << virt_pin))
+	if ((pic->mask & (1 << virt_pin)) != 0U)
 		return true;
 	else
 		return false;
@@ -364,7 +364,7 @@ static int vpic_ocw1(struct vpic *vpic, struct pic *pic, uint8_t val)
 		/* remap for active: interrupt mask -> unmask
 		 * remap for deactive: when vIOAPIC take it over
 		 */
-		if (((pic->mask & bit) == 0) && (old & bit)) {
+		if (((pic->mask & bit) == 0) && ((old & bit) != 0U)) {
 			struct ptdev_intx_info intx;
 
 			/* master pic pin2 connect with slave pic,
@@ -410,7 +410,7 @@ static int vpic_ocw2(struct vpic *vpic, struct pic *pic, uint8_t val)
 		}
 
 		/* if level ack PTDEV */
-		if (pic->elc & (1 << (isr_bit & 0x7))) {
+		if ((pic->elc & (1 << (isr_bit & 0x7))) != 0U) {
 			ptdev_intx_ack(vpic->vm,
 				master_pic(vpic, pic) ? isr_bit : isr_bit + 8,
 				PTDEV_VPIN_PIC);
@@ -428,14 +428,14 @@ static int vpic_ocw3(struct vpic *vpic, struct pic *pic, uint8_t val)
 	dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic ocw3 0x%x\n",
 		vpic->vm, val);
 
-	if (val & OCW3_ESMM) {
-		pic->smm = val & OCW3_SMM ? 1 : 0;
+	if ((val & OCW3_ESMM) != 0U) {
+		pic->smm = ((val & OCW3_SMM) != 0U) ? 1 : 0;
 		dev_dbg(ACRN_DBG_PIC, "%s pic special mask mode %s\n",
 		    master_pic(vpic, pic) ? "master" : "slave",
-		    pic->smm ?  "enabled" : "disabled");
+		    (pic->smm != 0U) ?  "enabled" : "disabled");
 	}
 
-	if (val & OCW3_RR) {
+	if ((val & OCW3_RR) != 0U) {
 		/* read register command */
 		pic->rd_cmd_reg = val & OCW3_RIS;
 
@@ -515,7 +515,7 @@ static int vpic_set_irqstate(struct vm *vm, uint32_t irq, enum irqstate irqstate
 		vpic_set_pinstate(vpic, irq, false);
 		break;
 	default:
-		ASSERT(0, "vpic_set_irqstate: invalid irqstate");
+		ASSERT(false, "vpic_set_irqstate: invalid irqstate");
 	}
 	VPIC_UNLOCK(vpic);
 
@@ -582,10 +582,10 @@ int vpic_get_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger *trigger
 		return -EINVAL;
 
 	vpic = vm_pic(vm);
-	if (!vpic)
+	if (vpic == NULL)
 		return -EINVAL;
 
-	if (vpic->pic[irq>>3].elc & (1 << (irq & 0x7)))
+	if ((vpic->pic[irq>>3].elc & (1 << (irq & 0x7))) != 0U)
 		*trigger = LEVEL_TRIGGER;
 	else
 		*trigger = EDGE_TRIGGER;
@@ -689,7 +689,7 @@ static int vpic_read(struct vpic *vpic, struct pic *pic,
 			*eax = 0;
 		}
 	} else {
-		if (port & ICU_IMR_OFFSET) {
+		if ((port & ICU_IMR_OFFSET) != 0) {
 			/* read interrupt mask register */
 			*eax = pic->mask;
 		} else {
@@ -719,7 +719,7 @@ static int vpic_write(struct vpic *vpic, struct pic *pic,
 
 	VPIC_LOCK(vpic);
 
-	if (port & ICU_IMR_OFFSET) {
+	if ((port & ICU_IMR_OFFSET) != 0) {
 		switch (pic->icw_num) {
 		case 2:
 			error = vpic_icw2(vpic, pic, val);
@@ -735,11 +735,11 @@ static int vpic_write(struct vpic *vpic, struct pic *pic,
 			break;
 		}
 	} else {
-		if (val & (1 << 4))
+		if ((val & (1 << 4)) != 0U)
 			error = vpic_icw1(vpic, pic, val);
 
 		if (pic->ready) {
-			if (val & (1 << 3))
+			if ((val & (1 << 3)) != 0U)
 				error = vpic_ocw3(vpic, pic, val);
 			else
 				error = vpic_ocw2(vpic, pic, val);
@@ -938,7 +938,7 @@ void *vpic_init(struct vm *vm)
 
 void vpic_cleanup(struct vm *vm)
 {
-	if (vm->vpic) {
+	if (vm->vpic != NULL) {
 		free(vm->vpic);
 		vm->vpic = NULL;
 	}