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DM: tpm: remove fixed value TPM_CRB_MMIO_ADDR

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The GPA of TPM device has fixed value TPM_CRB_MMIO_ADDR, remove
TPM_CRB_MMIO_ADDR and allocate GPA base for TPM device

Tracked-On: #5913
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit is contained in:
Tao Yuhong
2021-04-19 09:38:40 -04:00
committed by wenlingz
parent f1c2eca1dc
commit cb8a6a7514
6 changed files with 68 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
devicemodel/include/mmio_dev.h
View File

@@ -15,6 +15,7 @@ int init_mmio_devs(struct vmctx *ctx);
void deinit_mmio_devs(struct vmctx *ctx);
int mmio_dev_alloc_gpa_resource32(uint32_t *addr, uint32_t size_in);
uint64_t get_mmio_dev_tpm2_base_gpa(void);
#define MMIO_DEV_BASE 0xF0000000U
#define MMIO_DEV_LIMIT 0xFE000000U

47
devicemodel/include/tpm.h
View File

@@ -11,32 +11,35 @@
#define TPM_CRB_MMIO_ADDR 0xFED40000UL
#define TPM_CRB_MMIO_SIZE 0x5000U
uint32_t get_vtpm_crb_mmio_addr(void);
uint32_t get_tpm_crb_mmio_addr(void);
/* TPM CRB registers */
enum {
CRB_REGS_LOC_STATE = TPM_CRB_MMIO_ADDR + 0x00,
CRB_REGS_RESERVED0 = TPM_CRB_MMIO_ADDR + 0x04,
CRB_REGS_LOC_CTRL = TPM_CRB_MMIO_ADDR + 0x08,
CRB_REGS_LOC_STS = TPM_CRB_MMIO_ADDR + 0x0C,
CRB_REGS_RESERVED1 = TPM_CRB_MMIO_ADDR + 0x10,
CRB_REGS_INTF_ID_LO = TPM_CRB_MMIO_ADDR + 0x30,
CRB_REGS_INTF_ID_HI = TPM_CRB_MMIO_ADDR + 0x34,
CRB_REGS_CTRL_EXT_LO = TPM_CRB_MMIO_ADDR + 0x38,
CRB_REGS_CTRL_EXT_HI = TPM_CRB_MMIO_ADDR + 0x3C,
CRB_REGS_CTRL_REQ = TPM_CRB_MMIO_ADDR + 0x40,
CRB_REGS_CTRL_STS = TPM_CRB_MMIO_ADDR + 0x44,
CRB_REGS_CTRL_CANCEL = TPM_CRB_MMIO_ADDR + 0x48,
CRB_REGS_CTRL_START = TPM_CRB_MMIO_ADDR + 0x4C,
CRB_REGS_CTRL_INT_ENABLE = TPM_CRB_MMIO_ADDR + 0x50,
CRB_REGS_CTRL_INT_STS = TPM_CRB_MMIO_ADDR + 0x54,
CRB_REGS_CTRL_CMD_SIZE = TPM_CRB_MMIO_ADDR + 0x58,
CRB_REGS_CTRL_CMD_PA_LO = TPM_CRB_MMIO_ADDR + 0x5C,
CRB_REGS_CTRL_CMD_PA_HI = TPM_CRB_MMIO_ADDR + 0x60,
CRB_REGS_CTRL_RSP_SIZE = TPM_CRB_MMIO_ADDR + 0x64,
CRB_REGS_CTRL_RSP_PA = TPM_CRB_MMIO_ADDR + 0x68,
CRB_DATA_BUFFER = TPM_CRB_MMIO_ADDR + 0x80
CRB_REGS_LOC_STATE = 0x00,
CRB_REGS_RESERVED0 = 0x04,
CRB_REGS_LOC_CTRL = 0x08,
CRB_REGS_LOC_STS = 0x0C,
CRB_REGS_RESERVED1 = 0x10,
CRB_REGS_INTF_ID_LO = 0x30,
CRB_REGS_INTF_ID_HI = 0x34,
CRB_REGS_CTRL_EXT_LO = 0x38,
CRB_REGS_CTRL_EXT_HI = 0x3C,
CRB_REGS_CTRL_REQ = 0x40,
CRB_REGS_CTRL_STS = 0x44,
CRB_REGS_CTRL_CANCEL = 0x48,
CRB_REGS_CTRL_START = 0x4C,
CRB_REGS_CTRL_INT_ENABLE = 0x50,
CRB_REGS_CTRL_INT_STS = 0x54,
CRB_REGS_CTRL_CMD_SIZE = 0x58,
CRB_REGS_CTRL_CMD_PA_LO = 0x5C,
CRB_REGS_CTRL_CMD_PA_HI = 0x60,
CRB_REGS_CTRL_RSP_SIZE = 0x64,
CRB_REGS_CTRL_RSP_PA = 0x68,
CRB_DATA_BUFFER = 0x80
};
#define TPM_CRB_REG_SIZE ((CRB_DATA_BUFFER) - (TPM_CRB_MMIO_ADDR))
#define TPM_CRB_REG_SIZE (CRB_DATA_BUFFER)
#define TPM_CRB_DATA_BUFFER_SIZE ((TPM_CRB_MMIO_SIZE) - (TPM_CRB_REG_SIZE))
/* APIs by tpm.c */