diff --git a/hypervisor/arch/x86/cpu.c b/hypervisor/arch/x86/cpu.c
index 5370eabe5..74c618c8a 100644
--- a/hypervisor/arch/x86/cpu.c
+++ b/hypervisor/arch/x86/cpu.c
@@ -26,6 +26,7 @@
 #include <cat.h>
 #include <vboot.h>
 #include <sgx.h>
+#include <uart16550.h>
 
 #define CPU_UP_TIMEOUT		100U /* millisecond */
 #define CPU_DOWN_TIMEOUT	100U /* millisecond */
@@ -106,6 +107,14 @@ void init_pcpu_pre(bool is_bsp)
 		/* Clear BSS */
 		(void)memset(&ld_bss_start, 0U, (size_t)(&ld_bss_end - &ld_bss_start));
 
+		(void)parse_hv_cmdline();
+		/*
+		 * WARNNING: here assume that vaddr2paddr is identical mapping.
+		 * Enable UART as early as possible.
+		 * Then we could use printf for debugging on early boot stage.
+		 */
+		uart16550_init(true);
+
 		/* Get CPU capabilities thru CPUID, including the physical address bit
 		 * limit which is required for initializing paging.
 		 */
diff --git a/hypervisor/boot/guest/deprivilege_boot.c b/hypervisor/boot/guest/deprivilege_boot.c
index b39591fc2..9c92df0cf 100644
--- a/hypervisor/boot/guest/deprivilege_boot.c
+++ b/hypervisor/boot/guest/deprivilege_boot.c
@@ -26,8 +26,6 @@ static void init_depri_boot(void)
 	struct multiboot_info *mbi = NULL;
 
 	if (!depri_initialized) {
-		(void)parse_hv_cmdline();
-
 		mbi = (struct multiboot_info *) hpa2hva(((uint64_t)(uint32_t)boot_regs[1]));
 		if ((mbi == NULL) || ((mbi->mi_flags & MULTIBOOT_INFO_HAS_DRIVES) == 0U)) {
 			pr_err("no multiboot drivers for depri_boot found");
diff --git a/hypervisor/debug/console.c b/hypervisor/debug/console.c
index caceedadd..3390a9c62 100644
--- a/hypervisor/debug/console.c
+++ b/hypervisor/debug/console.c
@@ -24,7 +24,7 @@ uint16_t console_vmid = ACRN_INVALID_VMID;
 
 void console_init(void)
 {
-	uart16550_init();
+	uart16550_init(false);
 }
 
 void console_putc(const char *ch)
diff --git a/hypervisor/debug/uart16550.c b/hypervisor/debug/uart16550.c
index 11bd859ae..98837a6b2 100644
--- a/hypervisor/debug/uart16550.c
+++ b/hypervisor/debug/uart16550.c
@@ -131,12 +131,17 @@ static void uart16550_set_baud_rate(uint32_t baud_rate)
 	uart16550_write_reg(uart, temp_reg, UART16550_LCR);
 }
 
-void uart16550_init(void)
+void uart16550_init(bool eraly_boot)
 {
 	if (!uart.enabled) {
 		return;
 	}
 
+	if (!eraly_boot && !uart.serial_port_mapped) {
+		hv_access_memory_region_update((uint64_t)uart.mmio_base_vaddr, PDE_SIZE);
+		return;
+	}
+
 	/* if configure serial PCI BDF, get its base MMIO address */
 	if (!uart.serial_port_mapped) {
 		serial_pci_bdf.value = get_pci_bdf_value(pci_bdf_info);
@@ -144,10 +149,6 @@ void uart16550_init(void)
 			hpa2hva(pci_pdev_read_cfg(serial_pci_bdf, pci_bar_offset(0), 4U) & PCIM_BAR_MEM_BASE);
 	}
 
-	if (!uart.serial_port_mapped) {
-		hv_access_memory_region_update((uint64_t)uart.mmio_base_vaddr, PDE_SIZE);
-	}
-
 	spinlock_init(&uart.rx_lock);
 	spinlock_init(&uart.tx_lock);
 	/* Enable TX and RX FIFOs */
diff --git a/hypervisor/include/debug/uart16550.h b/hypervisor/include/debug/uart16550.h
index fe4b84f62..5181fb2c5 100644
--- a/hypervisor/include/debug/uart16550.h
+++ b/hypervisor/include/debug/uart16550.h
@@ -127,7 +127,7 @@
 /* UART oscillator clock */
 #define UART_CLOCK_RATE	1843200U	/* 1.8432 MHz */
 
-void uart16550_init(void);
+void uart16550_init(bool early_boot);
 char uart16550_getc(void);
 size_t uart16550_puts(const char *buf, uint32_t len);
 void uart16550_set_property(bool enabled, bool port_mapped, uint64_t base_addr);
diff --git a/hypervisor/release/uart16550.c b/hypervisor/release/uart16550.c
new file mode 100644
index 000000000..bdf762b62
--- /dev/null
+++ b/hypervisor/release/uart16550.c
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <types.h>
+
+void uart16550_init(__unused bool early_boot) {}