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hv: CAT is supposed to be enabled in the system level

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In platforms that support CAT, when it is enabled by ACRN, i.e.
IA32_resourceType_MASK_n registers are programmed with customized values,
it has impacts to the whole system.

The per guest flag GUEST_FLAG_CLOS_REQUIRED suggests that CAT may be
enabled in some guests, but not in others who don't have this flag,
which is conceptually incorrect.

This patch removes GUEST_FLAG_CLOS_REQUIRED, and adds a new Kconfig
entry CAT_ENABLED for CAT enabling. When it's enabled, platform_clos_array[]
defines a set of system-wide Class of Service (COS, or CLOS), and the
per guest vm_configs[].clos associates the guest with particular CLOS.

Tracked-On: #2462
Signed-off-by: Zide Chen <zide.chen@intel.com>
This commit is contained in:
Zide Chen 2020-02-05 10:23:07 -08:00 committed by wenlingz
parent 8dcede7693
commit cc6f094926
7 changed files with 21 additions and 14 deletions
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8
hypervisor/arch/x86/Kconfig
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@ -244,6 +244,14 @@ config HYPERV_ENABLED
When set, the minimum set of TLFS functionality together with some When set, the minimum set of TLFS functionality together with some
performance enlightenments are enabled. performance enlightenments are enabled.
config CAT_ENABLED
bool "Enable CAT (Cache Allocation Technology)"
default n
help
When set in platforms that support CAT, hypervisor can allocate
various amount of last-level-cache (LLC) resources to VMs to achieve
different Class of Service (COS, or CLOS).
config GPU_SBDF config GPU_SBDF
hex "Segment, Bus, Device, and function of the GPU" hex "Segment, Bus, Device, and function of the GPU"
depends on ACPI_PARSE_ENABLED depends on ACPI_PARSE_ENABLED

2
hypervisor/arch/x86/cat.c
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@ -37,7 +37,7 @@ int32_t init_cat_cap_info(void)
cat_cap_info.res_id = CAT_RESID_L2; cat_cap_info.res_id = CAT_RESID_L2;
} }
cat_cap_info.support = true; cat_cap_info.enabled = true;
/* CPUID.(EAX=0x10,ECX=ResID):EAX[4:0] reports the length of CBM supported /* CPUID.(EAX=0x10,ECX=ResID):EAX[4:0] reports the length of CBM supported
* CPUID.(EAX=0x10,ECX=ResID):EBX[31:0] indicates the corresponding uints * CPUID.(EAX=0x10,ECX=ResID):EBX[31:0] indicates the corresponding uints

9
hypervisor/arch/x86/configs/vm_config.c
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@ -184,14 +184,11 @@ bool sanitize_vm_config(void)
break; break;
} }
if ((vm_config->guest_flags & GUEST_FLAG_CLOS_REQUIRED) != 0U) { if (cat_cap_info.enabled && (vm_config->clos > cat_cap_info.clos_max)) {
if (cat_cap_info.support && (vm_config->clos <= cat_cap_info.clos_max)) { pr_err("%s set CLOS(%d) more than system supports(%d)\n", __func__,
cat_cap_info.enabled = true; vm_config->clos, cat_cap_info.clos_max);
} else {
pr_err("%s set wrong CLOS or CAT is not supported\n", __func__);
ret = false; ret = false;
} }
}
if (((vm_config->epc.size | vm_config->epc.base) & ~PAGE_MASK) != 0UL) { if (((vm_config->epc.size | vm_config->epc.base) & ~PAGE_MASK) != 0UL) {
ret = false; ret = false;

2
hypervisor/arch/x86/cpu.c
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@ -149,10 +149,12 @@ void init_pcpu_pre(bool is_bsp)
panic("System IOAPIC info is incorrect!"); panic("System IOAPIC info is incorrect!");
} }
#ifdef CONFIG_CAT_ENABLED
ret = init_cat_cap_info(); ret = init_cat_cap_info();
if (ret != 0) { if (ret != 0) {
panic("Platform CAT info is incorrect!"); panic("Platform CAT info is incorrect!");
} }
#endif
/* NOTE: this must call after MMCONFIG is parsed in init_vboot and before APs are INIT. */ /* NOTE: this must call after MMCONFIG is parsed in init_vboot and before APs are INIT. */
pci_switch_to_mmio_cfg_ops(); pci_switch_to_mmio_cfg_ops();

3
hypervisor/include/arch/x86/cat.h
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@ -9,8 +9,7 @@
/* The intel Resource Director Tech(RDT) based Cache Allocation Tech support */ /* The intel Resource Director Tech(RDT) based Cache Allocation Tech support */
struct cat_hw_info { struct cat_hw_info {
bool support; /* If L2/L3 CAT supported */ bool enabled; /* If L2/L3 CAT enabled */
bool enabled; /* If any VM setup CLOS */
uint32_t bitmask; /* Used by other entities */ uint32_t bitmask; /* Used by other entities */
uint16_t cbm_len; /* Length of Cache mask in bits */ uint16_t cbm_len; /* Length of Cache mask in bits */
uint16_t clos_max; /* Maximum CLOS supported, the number of cache masks */ uint16_t clos_max; /* Maximum CLOS supported, the number of cache masks */

4
hypervisor/include/arch/x86/vm_config.h
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@ -127,7 +127,9 @@ struct acrn_vm_config {
uint16_t pci_dev_num; /* indicate how many PCI devices in VM */ uint16_t pci_dev_num; /* indicate how many PCI devices in VM */
struct acrn_vm_pci_dev_config *pci_devs; /* point to PCI devices BDF list */ struct acrn_vm_pci_dev_config *pci_devs; /* point to PCI devices BDF list */
struct acrn_vm_os_config os_config; /* OS information the VM */ struct acrn_vm_os_config os_config; /* OS information the VM */
uint16_t clos; /* if guest_flags has GUEST_FLAG_CLOS_REQUIRED, then VM use this CLOS */ uint16_t clos; /* Class of Service, effective only if CONFIG_CAT_ENABLED
* is defined on CAT capable platforms
*/
struct vuart_config vuart[MAX_VUART_NUM_PER_VM];/* vuart configuration for VM */ struct vuart_config vuart[MAX_VUART_NUM_PER_VM];/* vuart configuration for VM */
} __aligned(8); } __aligned(8);

5
hypervisor/include/public/acrn_common.h
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@ -50,9 +50,8 @@
#define GUEST_FLAG_SECURE_WORLD_ENABLED (1UL << 0U) /* Whether secure world is enabled */ #define GUEST_FLAG_SECURE_WORLD_ENABLED (1UL << 0U) /* Whether secure world is enabled */
#define GUEST_FLAG_LAPIC_PASSTHROUGH (1UL << 1U) /* Whether LAPIC is passed through */ #define GUEST_FLAG_LAPIC_PASSTHROUGH (1UL << 1U) /* Whether LAPIC is passed through */
#define GUEST_FLAG_IO_COMPLETION_POLLING (1UL << 2U) /* Whether need hypervisor poll IO completion */ #define GUEST_FLAG_IO_COMPLETION_POLLING (1UL << 2U) /* Whether need hypervisor poll IO completion */
#define GUEST_FLAG_CLOS_REQUIRED (1UL << 3U) /* Whether CLOS is required */ #define GUEST_FLAG_HIDE_MTRR (1UL << 3U) /* Whether hide MTRR from VM */
#define GUEST_FLAG_HIDE_MTRR (1UL << 4U) /* Whether hide MTRR from VM */ #define GUEST_FLAG_RT (1UL << 4U) /* Whether the vm is RT-VM */
#define GUEST_FLAG_RT (1UL << 5U) /* Whether the vm is RT-VM */
/* TODO: We may need to get this addr from guest ACPI instead of hardcode here */ /* TODO: We may need to get this addr from guest ACPI instead of hardcode here */
#define VIRTUAL_PM1A_CNT_ADDR 0x404U #define VIRTUAL_PM1A_CNT_ADDR 0x404U