github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-06-25 15:02:13 +00:00
Code Issues Projects Releases Wiki Activity

HV: cleanup coding style violation

Browse Source 
- replace MACROs with inline functions
 - remove unused local viarbles
 - fix build errors

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Yonghua Huang 2018-07-05 01:30:18 +08:00 committed by lijinxia
parent b0deb1b5bd
commit cc7167026b
5 changed files with 33 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hypervisor/arch/x86/guest/vioapic.c
View File

@ -536,7 +536,6 @@ vioapic_reset(struct vioapic *vioapic)
struct vioapic * struct vioapic *
vioapic_init(struct vm *vm) vioapic_init(struct vm *vm)
{ {
int i;
struct vioapic *vioapic; struct vioapic *vioapic;
vioapic = calloc(1, sizeof(struct vioapic)); vioapic = calloc(1, sizeof(struct vioapic));

62
hypervisor/arch/x86/guest/vlapic.c
View File

@ -49,34 +49,28 @@
#define ACRN_DBG_LAPIC 6 #define ACRN_DBG_LAPIC 6
#if VLAPIC_VERBOS #if VLAPIC_VERBOS
#define VLAPIC_CTR_IRR(vlapic, msg) \ static inline void vlapic_dump_irr(struct vlapic *vlapic, char *msg)
do { \ {
struct lapic_reg *irrptr = &(vlapic)->apic_page->irr[0]; \ int i;
dev_dbg(ACRN_DBG_LAPIC, msg " irr0 0x%08x", irrptr[0].val); \ struct lapic_reg *irrptr = &(vlapic)->apic_page->irr[0];
dev_dbg(ACRN_DBG_LAPIC, msg " irr1 0x%08x", irrptr[1].val); \
dev_dbg(ACRN_DBG_LAPIC, msg " irr2 0x%08x", irrptr[2].val); \
dev_dbg(ACRN_DBG_LAPIC, msg " irr3 0x%08x", irrptr[3].val); \
dev_dbg(ACRN_DBG_LAPIC, msg " irr4 0x%08x", irrptr[4].val); \
dev_dbg(ACRN_DBG_LAPIC, msg " irr5 0x%08x", irrptr[5].val); \
dev_dbg(ACRN_DBG_LAPIC, msg " irr6 0x%08x", irrptr[6].val); \
dev_dbg(ACRN_DBG_LAPIC, msg " irr7 0x%08x", irrptr[7].val); \
} while (0)
#define VLAPIC_CTR_ISR(vlapic, msg) \ for (i = 0; i < 8; i++)
do { \ dev_dbg(ACRN_DBG_LAPIC, "%s irr%d 0x%08x",
struct lapic_reg *isrptr = &(vlapic)->apic_page->isr[0]; \ msg, i, irrptr[i].val);
dev_dbg(ACRN_DBG_LAPIC, msg " isr0 0x%08x", isrptr[0].val); \ }
dev_dbg(ACRN_DBG_LAPIC, msg " isr1 0x%08x", isrptr[1].val); \
dev_dbg(ACRN_DBG_LAPIC, msg " isr2 0x%08x", isrptr[2].val); \ static inline void vlapic_dump_isr(struct vlapic *vlapic, char *msg)
dev_dbg(ACRN_DBG_LAPIC, msg " isr3 0x%08x", isrptr[3].val); \ {
dev_dbg(ACRN_DBG_LAPIC, msg " isr4 0x%08x", isrptr[4].val); \ int i;
dev_dbg(ACRN_DBG_LAPIC, msg " isr5 0x%08x", isrptr[5].val); \ struct lapic_reg *isrptr = &(vlapic)->apic_page->isr[0];
dev_dbg(ACRN_DBG_LAPIC, msg " isr6 0x%08x", isrptr[6].val); \
dev_dbg(ACRN_DBG_LAPIC, msg " isr7 0x%08x", isrptr[7].val); \ for (i = 0; i < 8; i++)
} while (0) dev_dbg(ACRN_DBG_LAPIC, "%s isr%d 0x%08x",
msg, i, isrptr[0].val);
}
#else #else
#define VLAPIC_CTR_IRR(vlapic, msg) #define vlapic_dump_irr(vlapic, msg)
#define VLAPIC_CTR_ISR(vlapic, msg) #define vlapic_dump_isr(vlapic, msg)
#endif #endif
/*APIC-v APIC-access address */ /*APIC-v APIC-access address */
@ -481,14 +475,14 @@ vlapic_set_intr_ready(struct vlapic *vlapic, uint32_t vector, bool level)
idx, tmrptr[idx].val, level ? "level" : "edge"); idx, tmrptr[idx].val, level ? "level" : "edge");
} }
VLAPIC_CTR_IRR(vlapic, "vlapic_set_intr_ready"); vlapic_dump_irr(vlapic, "vlapic_set_intr_ready");
return 1; return 1;
} }
static inline int static inline int
lvt_off_to_idx(uint32_t offset) lvt_off_to_idx(uint32_t offset)
{ {
int index; uint32_t index = -1U;
switch (offset) { switch (offset) {
case APIC_OFFSET_CMCI_LVT: case APIC_OFFSET_CMCI_LVT:
@ -513,10 +507,9 @@ lvt_off_to_idx(uint32_t offset)
index = APIC_LVT_ERROR; index = APIC_LVT_ERROR;
break; break;
default: default:
index = -1;
break; break;
} }
ASSERT(index >= 0 && index <= VLAPIC_MAXLVT_INDEX, ASSERT(index <= VLAPIC_MAXLVT_INDEX,
"%s: invalid lvt index %d for offset %#x", "%s: invalid lvt index %d for offset %#x",
__func__, index, offset); __func__, index, offset);
@ -783,7 +776,7 @@ vlapic_process_eoi(struct vlapic *vlapic)
isrptr[i].val &= ~(1U << (uint32_t)bitpos); isrptr[i].val &= ~(1U << (uint32_t)bitpos);
vector = i * 32 + (int32_t)bitpos; vector = i * 32 + (int32_t)bitpos;
dev_dbg(ACRN_DBG_LAPIC, "EOI vector %d", vector); dev_dbg(ACRN_DBG_LAPIC, "EOI vector %d", vector);
VLAPIC_CTR_ISR(vlapic, "vlapic_process_eoi"); vlapic_dump_isr(vlapic, "vlapic_process_eoi");
vlapic->isrvec_stk_top--; vlapic->isrvec_stk_top--;
vlapic_update_ppr(vlapic); vlapic_update_ppr(vlapic);
if ((tmrptr[i].val & (1U << (uint32_t)bitpos)) != 0U) { if ((tmrptr[i].val & (1U << (uint32_t)bitpos)) != 0U) {
@ -1179,11 +1172,11 @@ vlapic_intr_accepted(struct vlapic *vlapic, uint32_t vector)
irrptr = &lapic->irr[0]; irrptr = &lapic->irr[0];
atomic_clear_int(&irrptr[idx].val, 1 << (vector % 32)); atomic_clear_int(&irrptr[idx].val, 1 << (vector % 32));
VLAPIC_CTR_IRR(vlapic, "vlapic_intr_accepted"); vlapic_dump_irr(vlapic, "vlapic_intr_accepted");
isrptr = &lapic->isr[0]; isrptr = &lapic->isr[0];
isrptr[idx].val |= 1U << (vector % 32); isrptr[idx].val |= 1U << (vector % 32);
VLAPIC_CTR_ISR(vlapic, "vlapic_intr_accepted"); vlapic_dump_isr(vlapic, "vlapic_intr_accepted");
/* /*
* Update the PPR * Update the PPR
@ -1528,8 +1521,7 @@ void
vlapic_init(struct vlapic *vlapic) vlapic_init(struct vlapic *vlapic)
{ {
ASSERT(vlapic->vm != NULL, "%s: vm is not initialized", __func__); ASSERT(vlapic->vm != NULL, "%s: vm is not initialized", __func__);
ASSERT(vlapic->vcpu->vcpu_id >= 0U && ASSERT(vlapic->vcpu->vcpu_id < phys_cpu_num,
vlapic->vcpu->vcpu_id < phys_cpu_num,
"%s: vcpu_id is not initialized", __func__); "%s: vcpu_id is not initialized", __func__);
ASSERT(vlapic->apic_page != NULL, ASSERT(vlapic->apic_page != NULL,
"%s: apic_page is not initialized", __func__); "%s: apic_page is not initialized", __func__);

6
hypervisor/arch/x86/ioapic.c
View File

@ -310,9 +310,9 @@ void setup_ioapic_irq(void)
for (ioapic_id = 0U; for (ioapic_id = 0U;
ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) { ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
int pin; uint32_t pin;
int max_pins; uint32_t max_pins;
int version; uint32_t version;
void *addr; void *addr;
addr = map_ioapic(get_ioapic_base(ioapic_id)); addr = map_ioapic(get_ioapic_base(ioapic_id));

1
hypervisor/arch/x86/pm.c
View File

@ -74,7 +74,6 @@ int enter_s3(struct vm *vm, uint32_t pm1a_cnt_val,
uint32_t pm1b_cnt_val) uint32_t pm1b_cnt_val)
{ {
uint32_t pcpu_id; uint32_t pcpu_id;
int ret;
uint64_t pmain_entry_saved; uint64_t pmain_entry_saved;
uint32_t guest_wakeup_vec32; uint32_t guest_wakeup_vec32;
uint64_t *pmain_entry; uint64_t *pmain_entry;

4
hypervisor/debug/shell_internal.c
View File

@ -317,7 +317,7 @@ int shell_process_cmd(struct shell *p_shell, char *p_input_line)
(void) string_to_argv(&cmd_argv_str[0], (void) string_to_argv(&cmd_argv_str[0],
(void *) &cmd_argv_mem[0], (void *) &cmd_argv_mem[0],
sizeof(cmd_argv_mem), &cmd_argc, &cmd_argv); sizeof(cmd_argv_mem), (void *)&cmd_argc, &cmd_argv);
/* Determine if there is a command to process. */ /* Determine if there is a command to process. */
if (cmd_argc != 0) { if (cmd_argc != 0) {
@ -1068,6 +1068,8 @@ int shell_trigger_crash(struct shell *p_shell, int argc, char **argv)
{ {
char str[MAX_STR_SIZE] = {0}; char str[MAX_STR_SIZE] = {0};
(void)argc;
(void)argv;
snprintf(str, MAX_STR_SIZE, "trigger crash, divide by 0 ...\r\n"); snprintf(str, MAX_STR_SIZE, "trigger crash, divide by 0 ...\r\n");
shell_puts(p_shell, str); shell_puts(p_shell, str);
snprintf(str, MAX_STR_SIZE, "%d\r", 1/0); snprintf(str, MAX_STR_SIZE, "%d\r", 1/0);