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https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-19 20:22:46 +00:00
HV: vpic: add suffix 'U' to constants in unsigned contexts
Constants represented in an unsigned type should have the 'U' suffix per MISRA C requirements even for 0 to get rid of implicit signedness conversions which can be confusing due to the implementation-defined integer formats. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Junjie Mao
lijinxia
parent
aadd81941d
commit
ccc222d193
@ -109,7 +109,7 @@ static inline uint8_t vpic_get_highest_isrpin(struct pic *pic)
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* An IS bit that is masked by an IMR bit will not be
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* cleared by a non-specific EOI in Special Mask Mode.
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*/
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if ((pic->smm != 0U) && (pic->mask & bit) != 0)
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if ((pic->smm != 0U) && (pic->mask & bit) != 0U)
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continue;
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else
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return pin;
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@ -139,7 +139,7 @@ static inline uint8_t vpic_get_highest_irrpin(struct pic *pic)
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* bearing on the levels that can generate interrupts.
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*/
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if (pic->smm != 0U)
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serviced = 0;
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serviced = 0U;
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PIC_PIN_FOREACH(pin, pic, tmp) {
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bit = (uint8_t)(1U << pin);
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@ -237,7 +237,7 @@ static void vpic_notify_intr(struct vpic *vpic)
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* to vioapic pin0 (irq2)
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* From MPSpec session 5.1
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*/
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vioapic_pulse_irq(vpic->vm, 0);
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vioapic_pulse_irq(vpic->vm, 0U);
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}
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} else {
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dev_dbg(ACRN_DBG_PIC,
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@ -254,19 +254,19 @@ static int vpic_icw1(struct vpic *vpic, struct pic *pic, uint8_t val)
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pic->ready = false;
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pic->icw_num = 1U;
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pic->request = 0;
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pic->mask = 0;
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pic->lowprio = 7;
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pic->request = 0U;
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pic->mask = 0U;
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pic->lowprio = 7U;
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pic->rd_cmd_reg = 0U;
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pic->poll = false;
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pic->smm = 0;
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pic->smm = 0U;
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if ((val & ICW1_SNGL) != 0) {
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dev_dbg(ACRN_DBG_PIC, "vpic cascade mode required\n");
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return -1;
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}
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if ((val & ICW1_IC4) == 0) {
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if ((val & ICW1_IC4) == 0U) {
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dev_dbg(ACRN_DBG_PIC, "vpic icw4 required\n");
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return -1;
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}
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@ -303,16 +303,16 @@ static int vpic_icw4(struct vpic *vpic, struct pic *pic, uint8_t val)
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic icw4 0x%x\n",
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vpic->vm, val);
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if ((val & ICW4_8086) == 0) {
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if ((val & ICW4_8086) == 0U) {
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dev_dbg(ACRN_DBG_PIC,
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"vpic microprocessor mode required\n");
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return -1;
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}
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if ((val & ICW4_AEOI) != 0)
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if ((val & ICW4_AEOI) != 0U)
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pic->aeoi = true;
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if ((val & ICW4_SFNM) != 0) {
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if ((val & ICW4_SFNM) != 0U) {
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if (master_pic(vpic, pic)) {
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pic->sfn = true;
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} else {
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@ -332,15 +332,15 @@ bool vpic_is_pin_mask(struct vpic *vpic, uint8_t virt_pin)
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{
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struct pic *pic;
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if (virt_pin < 8)
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if (virt_pin < 8U)
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pic = &vpic->pic[0];
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else if (virt_pin < 16) {
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else if (virt_pin < 16U) {
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pic = &vpic->pic[1];
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virt_pin -= 8;
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virt_pin -= 8U;
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} else
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return true;
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if ((pic->mask & (1 << virt_pin)) != 0U)
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if ((pic->mask & (1U << virt_pin)) != 0U)
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return true;
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else
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return false;
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@ -363,19 +363,19 @@ static int vpic_ocw1(struct vpic *vpic, struct pic *pic, uint8_t val)
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/* remap for active: interrupt mask -> unmask
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* remap for deactive: when vIOAPIC take it over
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*/
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if (((pic->mask & bit) == 0) && ((old & bit) != 0U)) {
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if (((pic->mask & bit) == 0U) && ((old & bit) != 0U)) {
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struct ptdev_intx_info intx;
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/* master pic pin2 connect with slave pic,
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* not device, so not need pt remap
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*/
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if ((pin == 2) && master_pic(vpic, pic))
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if ((pin == 2U) && master_pic(vpic, pic))
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continue;
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intx.virt_pin = pin;
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intx.vpin_src = PTDEV_VPIN_PIC;
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if (!master_pic(vpic, pic))
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intx.virt_pin += 8;
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intx.virt_pin += 8U;
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ptdev_intx_pin_remap(vpic->vm, &intx);
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}
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}
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@ -388,12 +388,12 @@ static int vpic_ocw2(struct vpic *vpic, struct pic *pic, uint8_t val)
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dev_dbg(ACRN_DBG_PIC, "vm 0x%x: pic ocw2 0x%x\n",
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vpic->vm, val);
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pic->rotate = ((val & OCW2_R) != 0);
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pic->rotate = ((val & OCW2_R) != 0U);
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if ((val & OCW2_EOI) != 0) {
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if ((val & OCW2_EOI) != 0U) {
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uint8_t isr_bit;
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if ((val & OCW2_SL) != 0) {
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if ((val & OCW2_SL) != 0U) {
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/* specific EOI */
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isr_bit = val & 0x7U;
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} else {
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@ -411,7 +411,7 @@ static int vpic_ocw2(struct vpic *vpic, struct pic *pic, uint8_t val)
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/* if level ack PTDEV */
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if ((pic->elc & (1U << (isr_bit & 0x7U))) != 0U) {
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ptdev_intx_ack(vpic->vm,
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master_pic(vpic, pic) ? isr_bit : isr_bit + 8,
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master_pic(vpic, pic) ? isr_bit : isr_bit + 8U,
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PTDEV_VPIN_PIC);
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}
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} else if ((val & OCW2_SL) != 0 && pic->rotate == true) {
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@ -428,7 +428,7 @@ static int vpic_ocw3(struct vpic *vpic, struct pic *pic, uint8_t val)
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vpic->vm, val);
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if ((val & OCW3_ESMM) != 0U) {
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pic->smm = ((val & OCW3_SMM) != 0U) ? 1 : 0;
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pic->smm = ((val & OCW3_SMM) != 0U) ? 1U : 0U;
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dev_dbg(ACRN_DBG_PIC, "%s pic special mask mode %s\n",
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master_pic(vpic, pic) ? "master" : "slave",
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(pic->smm != 0U) ? "enabled" : "disabled");
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@ -439,7 +439,7 @@ static int vpic_ocw3(struct vpic *vpic, struct pic *pic, uint8_t val)
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pic->rd_cmd_reg = val & OCW3_RIS;
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/* Polling mode */
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pic->poll = ((val & OCW3_P) != 0);
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pic->poll = ((val & OCW3_P) != 0U);
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}
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return 0;
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@ -454,7 +454,7 @@ static void vpic_set_pinstate(struct vpic *vpic, uint8_t pin, bool newstate)
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ASSERT(pin < NR_VPIC_PINS_TOTAL,
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"vpic_set_pinstate: invalid pin number");
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pic = &vpic->pic[pin >> 3];
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pic = &vpic->pic[pin >> 3U];
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oldcnt = pic->acnt[pin & 0x7U];
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if (newstate)
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@ -467,7 +467,7 @@ static void vpic_set_pinstate(struct vpic *vpic, uint8_t pin, bool newstate)
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pr_warn("pic pin%hhu: bad acnt %d\n", pin, newcnt);
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}
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level = ((vpic->pic[pin >> 3].elc & (1 << (pin & 0x7U))) != 0);
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level = ((vpic->pic[pin >> 3U].elc & (1U << (pin & 0x7U))) != 0);
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if ((oldcnt == 0 && newcnt == 1) || (newcnt > 0 && level == true)) {
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/* rising edge or level */
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@ -497,7 +497,7 @@ static int vpic_set_irqstate(struct vm *vm, uint32_t irq, enum irqstate irqstate
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return -EINVAL;
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vpic = vm_pic(vm);
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pic = &vpic->pic[irq >> 3];
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pic = &vpic->pic[irq >> 3U];
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pin = (uint8_t)irq;
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if (pic->ready == false)
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@ -553,11 +553,11 @@ int vpic_set_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger trigger)
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*/
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if (trigger == LEVEL_TRIGGER) {
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switch (irq) {
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case 0:
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case 1:
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case 2:
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case 8:
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case 13:
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case 0U:
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case 1U:
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case 2U:
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case 8U:
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case 13U:
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return -EINVAL;
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}
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}
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@ -588,7 +588,7 @@ int vpic_get_irq_trigger(struct vm *vm, uint32_t irq, enum vpic_trigger *trigger
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if (vpic == NULL)
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return -EINVAL;
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if ((vpic->pic[irq>>3].elc & (1U << (irq & 0x7U))) != 0U)
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if ((vpic->pic[irq >> 3U].elc & (1U << (irq & 0x7U))) != 0U)
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*trigger = LEVEL_TRIGGER;
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else
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*trigger = EDGE_TRIGGER;
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@ -608,7 +608,7 @@ void vpic_pending_intr(struct vm *vm, uint32_t *vecptr)
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VPIC_LOCK(vpic);
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pin = vpic_get_highest_irrpin(pic);
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if (pin == 2) {
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if (pin == 2U) {
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pic = &vpic->pic[1];
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pin = vpic_get_highest_irrpin(pic);
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}
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@ -634,7 +634,7 @@ static void vpic_pin_accepted(struct pic *pic, uint8_t pin)
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{
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pic->intr_raised = false;
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if ((pic->elc & (1 << pin)) == 0) {
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if ((pic->elc & (1U << pin)) == 0) {
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/*only used edge trigger mode*/
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pic->request &= ~(uint8_t)(1U << pin);
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}
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@ -691,7 +691,7 @@ static int vpic_read(struct vpic *vpic, struct pic *pic,
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*eax = 0U;
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}
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} else {
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if ((port & ICU_IMR_OFFSET) != 0) {
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if ((port & ICU_IMR_OFFSET) != 0U) {
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/* read interrupt mask register */
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*eax = pic->mask;
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} else {
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@ -721,7 +721,7 @@ static int vpic_write(struct vpic *vpic, struct pic *pic,
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VPIC_LOCK(vpic);
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if ((port & ICU_IMR_OFFSET) != 0) {
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if ((port & ICU_IMR_OFFSET) != 0U) {
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switch (pic->icw_num) {
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case 2U:
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error = vpic_icw2(vpic, pic, val);
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@ -737,11 +737,11 @@ static int vpic_write(struct vpic *vpic, struct pic *pic,
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break;
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}
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} else {
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if ((val & (1 << 4)) != 0U)
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if ((val & (1U << 4U)) != 0U)
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error = vpic_icw1(vpic, pic, val);
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if (pic->ready) {
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if ((val & (1 << 3)) != 0U)
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if ((val & (1U << 3U)) != 0U)
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error = vpic_ocw3(vpic, pic, val);
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else
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error = vpic_ocw2(vpic, pic, val);
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@ -777,7 +777,7 @@ static int vpic_master_handler(struct vm *vm, bool in, uint16_t port,
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static uint32_t vpic_master_io_read(__unused struct vm_io_handler *hdlr,
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struct vm *vm, uint16_t addr, size_t width)
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{
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uint32_t val = 0;
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uint32_t val = 0U;
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if (vpic_master_handler(vm, true, addr, width, &val) < 0)
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pr_err("pic master read port 0x%x width=%d failed\n",
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@ -816,7 +816,7 @@ static int vpic_slave_handler(struct vm *vm, bool in, uint16_t port,
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static uint32_t vpic_slave_io_read(__unused struct vm_io_handler *hdlr,
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struct vm *vm, uint16_t addr, size_t width)
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{
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uint32_t val = 0;
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uint32_t val = 0U;
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if (vpic_slave_handler(vm, true, addr, width, &val) < 0)
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pr_err("pic slave read port 0x%x width=%d failed\n",
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@ -878,7 +878,7 @@ static int vpic_elc_handler(struct vm *vm, bool in, uint16_t port, size_t bytes,
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static uint32_t vpic_elc_io_read(__unused struct vm_io_handler *hdlr,
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struct vm *vm, uint16_t addr, size_t width)
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{
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uint32_t val = 0;
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uint32_t val = 0U;
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if (vpic_elc_handler(vm, true, addr, width, &val) < 0)
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pr_err("pic elc read port 0x%x width=%d failed", addr, width);
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@ -899,18 +899,18 @@ void vpic_register_io_handler(struct vm *vm)
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{
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struct vm_io_range master_range = {
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.flags = IO_ATTR_RW,
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.base = 0x20,
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.len = 2
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.base = 0x20U,
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.len = 2U
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};
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struct vm_io_range slave_range = {
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.flags = IO_ATTR_RW,
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.base = 0xa0,
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.len = 2
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.base = 0xa0U,
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.len = 2U
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};
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struct vm_io_range elcr_range = {
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.flags = IO_ATTR_RW,
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.base = 0x4d0,
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.len = 2
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.base = 0x4d0U,
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.len = 2U
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};
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register_io_emulation_handler(vm, &master_range,
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@ -927,11 +927,11 @@ void *vpic_init(struct vm *vm)
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vpic_register_io_handler(vm);
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vpic = calloc(1, sizeof(struct vpic));
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vpic = calloc(1U, sizeof(struct vpic));
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ASSERT(vpic != NULL, "");
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vpic->vm = vm;
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vpic->pic[0].mask = 0xff;
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vpic->pic[1].mask = 0xff;
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vpic->pic[0].mask = 0xffU;
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vpic->pic[1].mask = 0xffU;
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VPIC_LOCK_INIT(vpic);
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