From cdfd35ed3d0970d83121df7e6540094d3fe393bb Mon Sep 17 00:00:00 2001 From: Haiwei Li Date: Thu, 7 Sep 2023 06:05:15 +0800 Subject: [PATCH] hv: s3: enable lapic earlier After Service VM OS resumes from s3, BSP starts APs asynchronously, followed by IPIs to APs to resume tsc. This process takes place in function `host_enter_s3`. While, APs' lapic are not ready to accept IPI interrupt, so BSP fails to resume tsc. So enable lapic earlier to make sure that APs are ready. Tracked-On: #8623 Signed-off-by: Haiwei Li --- hypervisor/arch/x86/lapic.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hypervisor/arch/x86/lapic.c b/hypervisor/arch/x86/lapic.c index 68bab1498..198d35abb 100644 --- a/hypervisor/arch/x86/lapic.c +++ b/hypervisor/arch/x86/lapic.c @@ -96,14 +96,6 @@ void early_init_lapic(void) /* Step2: Enable LAPIC in x2APIC mode */ base.fields.x2APIC_enable = 1U; msr_write(MSR_IA32_APIC_BASE, base.value); -} - -/** - * @pre pcpu_id < 8U - */ -void init_lapic(uint16_t pcpu_id) -{ - per_cpu(lapic_ldr, pcpu_id) = (uint32_t) msr_read(MSR_IA32_EXT_APIC_LDR); /* Set the mask bits for all the LVT entries by disabling a local APIC software. */ msr_write(MSR_IA32_EXT_APIC_SIVR, 0UL); @@ -116,6 +108,14 @@ void init_lapic(uint16_t pcpu_id) clear_lapic_isr(); } +void init_lapic(uint16_t pcpu_id) +{ + /* Can not put this to early_init_lapic because logical ID is not + * updated yet. + */ + per_cpu(lapic_ldr, pcpu_id) = (uint32_t) msr_read(MSR_IA32_EXT_APIC_LDR); +} + static void save_lapic(struct lapic_regs *regs) { regs->tpr.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TPR);