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HV: Add WhiskeyLake board configuration files

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This patch adds offline tool generated WhiskeyLake
board configurations files.

Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Vijay Dhanraj 2020-02-19 23:46:54 -08:00 committed by wenlingz
parent eaad91fd71
commit cef3322da8
6 changed files with 357 additions and 0 deletions
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10
hypervisor/arch/x86/configs/whl-ipc-i5.config Normal file
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# New board kconfig generated by vm config tool
# Modified by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
CONFIG_BOARD="whl-ipc-i5"
CONFIG_SERIAL_LEGACY=y
CONFIG_SERIAL_PIO_BASE=0x3F8
CONFIG_HV_RAM_START=0x11000000
CONFIG_HV_RAM_SIZE=0x7800000
CONFIG_RDT_ENABLED

97
hypervisor/arch/x86/configs/whl-ipc-i5/board.c Normal file
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/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* BIOS Information
* Vendor: American Megatrends Inc.
* Version: WL10R104
* Release Date: 09/12/2019
* BIOS Revision: 5.13
*
* Base Board Information
* Manufacturer: Maxtang
* Product Name: WL10
* Version: V1.0
*/
#include <board.h>
#include <vtd.h>
#include <msr.h>
#include <pci.h>
static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
{
.type = DRHD0_DEVSCOPE0_TYPE,
.id = DRHD0_DEVSCOPE0_ID,
.bus = DRHD0_DEVSCOPE0_BUS,
.devfun = DRHD0_DEVSCOPE0_PATH,
},
};
static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = {
{
.type = DRHD1_DEVSCOPE0_TYPE,
.id = DRHD1_DEVSCOPE0_ID,
.bus = DRHD1_DEVSCOPE0_BUS,
.devfun = DRHD1_DEVSCOPE0_PATH,
},
{
.type = DRHD1_DEVSCOPE1_TYPE,
.id = DRHD1_DEVSCOPE1_ID,
.bus = DRHD1_DEVSCOPE1_BUS,
.devfun = DRHD1_DEVSCOPE1_PATH,
},
};
static struct dmar_drhd drhd_info_array[DRHD_COUNT] = {
{
.dev_cnt = DRHD0_DEV_CNT,
.segment = DRHD0_SEGMENT,
.flags = DRHD0_FLAGS,
.reg_base_addr = DRHD0_REG_BASE,
.ignore = DRHD0_IGNORE,
.devices = drhd0_dev_scope
},
{
.dev_cnt = DRHD1_DEV_CNT,
.segment = DRHD1_SEGMENT,
.flags = DRHD1_FLAGS,
.reg_base_addr = DRHD1_REG_BASE,
.ignore = DRHD1_IGNORE,
.devices = drhd1_dev_scope
},
};
struct dmar_info plat_dmar_info = {
.drhd_count = DRHD_COUNT,
.drhd_units = drhd_info_array,
};
#ifdef CONFIG_RDT_ENABLED
struct platform_clos_info platform_l2_clos_array[MAX_PLATFORM_CLOS_NUM];
struct platform_clos_info platform_l3_clos_array[MAX_PLATFORM_CLOS_NUM];
#endif
static const struct cpu_cx_data board_cpu_cx[3] = {
{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */
{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x33UL}, 0x02U, 0x97U, 0x00U}, /* C2 */
{{SPACE_FFixedHW, 0x01U, 0x02U, 0x01U, 0x60UL}, 0x03U, 0x40AU, 0x00U}, /* C3 */
};
static const struct cpu_px_data board_cpu_px[6] = {
{0xBB9UL, 0x00UL, 0x0AUL, 0x0AUL, 0x002700UL, 0x002700UL}, /* P0 */
{0xBB8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001E00UL, 0x001E00UL}, /* P1 */
{0x708UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001200UL, 0x001200UL}, /* P2 */
{0x640UL, 0x00UL, 0x0AUL, 0x0AUL, 0x001000UL, 0x001000UL}, /* P3 */
{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P4 */
{0x3E8UL, 0x00UL, 0x0AUL, 0x0AUL, 0x000A00UL, 0x000A00UL}, /* P5 */
};
const struct cpu_state_table board_cpu_state_tbl = {
"Intel(R) Core(TM) i5-8265U CPU @ 1.60GHz",
{(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px,
(uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx}
};
const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];

20
hypervisor/arch/x86/configs/whl-ipc-i5/misc_cfg.h Normal file
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/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MISC_CFG_H
#define MISC_CFG_H
#define MAX_PCPU_NUM 4U
#define MAX_PLATFORM_CLOS_NUM 0U
#define ROOTFS_0 "root=/dev/nvme0n1p3 "
#define ROOTFS_1 "root=/dev/sda3 "
#define MAX_HIDDEN_PDEVS_NUM 0U
#endif /* MISC_CFG_H */

63
hypervisor/arch/x86/configs/whl-ipc-i5/pci_devices.h Normal file
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/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* BIOS Information
* Vendor: American Megatrends Inc.
* Version: WL10R104
* Release Date: 09/12/2019
* BIOS Revision: 5.13
*
* Base Board Information
* Manufacturer: Maxtang
* Product Name: WL10
* Version: V1.0
*/
#ifndef PCI_DEVICES_H_
#define PCI_DEVICES_H_
#define HOST_BRIDGE .pbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x00U}
#define VGA_COMPATIBLE_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x00U}, \
.vbar_base[0] = 0xa0000000UL, \
.vbar_base[2] = 0x90000000UL
#define SIGNAL_PROCESSING_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x12U, .f = 0x00U}, \
.vbar_base[0] = 0xa141e000UL
#define USB_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x00U}, \
.vbar_base[0] = 0xa1400000UL
#define RAM_MEMORY_0 .pbdf.bits = {.b = 0x00U, .d = 0x14U, .f = 0x02U}, \
.vbar_base[0] = 0xa1416000UL, \
.vbar_base[2] = 0xa141d000UL
#define COMMUNICATION_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x16U, .f = 0x00U}, \
.vbar_base[0] = 0xa141c000UL
#define SATA_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x17U, .f = 0x00U}, \
.vbar_base[0] = 0xa1414000UL, \
.vbar_base[1] = 0xa141b000UL, \
.vbar_base[5] = 0xa141a000UL
#define SD_HOST_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1AU, .f = 0x00U}, \
.vbar_base[0] = 0xa1419000UL
#define PCI_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x00U}
#define PCI_BRIDGE_1 .pbdf.bits = {.b = 0x00U, .d = 0x1CU, .f = 0x04U}
#define PCI_BRIDGE_2 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x00U}
#define PCI_BRIDGE_3 .pbdf.bits = {.b = 0x00U, .d = 0x1DU, .f = 0x01U}
#define ISA_BRIDGE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x00U}
#define AUDIO_DEVICE_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x03U}, \
.vbar_base[0] = 0xa1410000UL, \
.vbar_base[4] = 0xa1000000UL
#define SMBUS_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x04U}, \
.vbar_base[0] = 0xa1418000UL
#define SERIAL_BUS_CONTROLLER_0 .pbdf.bits = {.b = 0x00U, .d = 0x1FU, .f = 0x05U}, \
.vbar_base[0] = 0xfe010000UL
#define NON_VOLATILE_MEMORY_CONTROLLER_0 .pbdf.bits = {.b = 0x02U, .d = 0x00U, .f = 0x00U}, \
.vbar_base[0] = 0xa1300000UL
#define ETHERNET_CONTROLLER_0 .pbdf.bits = {.b = 0x03U, .d = 0x00U, .f = 0x00U}, \
.vbar_base[0] = 0xa1200000UL, \
.vbar_base[3] = 0xa1220000UL
#define ETHERNET_CONTROLLER_1 .pbdf.bits = {.b = 0x04U, .d = 0x00U, .f = 0x00U}, \
.vbar_base[0] = 0xa1100000UL, \
.vbar_base[3] = 0xa1120000UL
#endif /* PCI_DEVICES_H_ */

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hypervisor/arch/x86/configs/whl-ipc-i5/ve820.c Normal file
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/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <e820.h>
#include <vm.h>
#define VM0_VE820_ENTRIES_WHL_IPC_I5 5U
#define VM1_VE820_ENTRIES_WHL_IPC_I5 5U
static const struct e820_entry vm0_ve820_entry[VM0_VE820_ENTRIES_WHL_IPC_I5] = {
{ /* usable RAM under 1MB */
.baseaddr = 0x0UL,
.length = 0xF0000UL, /* 960KB */
.type = E820_TYPE_RAM
},
{ /* mptable */
.baseaddr = 0xF0000UL, /* 960KB */
.length = 0x10000UL, /* 64KB */
.type = E820_TYPE_RESERVED
},
{ /* lowmem */
.baseaddr = 0x100000UL, /* 1MB */
.length = 0x1ff00000UL, /* 511.0MB */
.type = E820_TYPE_RAM
},
{ /* between lowmem and PCI hole */
.baseaddr = 0x20000000UL, /* 512.0MB */
.length = 0xA0000000UL, /* 2560.0MB */
.type = E820_TYPE_RESERVED
},
{ /* between PCI hole and 4 GB */
.baseaddr = 0xe0000000UL, /* 3.5GB */
.length = 0x20000000UL, /* 512.0MB */
.type = E820_TYPE_RESERVED
},
};
static const struct e820_entry vm1_ve820_entry[VM1_VE820_ENTRIES_WHL_IPC_I5] = {
{ /* usable RAM under 1MB */
.baseaddr = 0x0UL,
.length = 0xF0000UL, /* 960KB */
.type = E820_TYPE_RAM
},
{ /* mptable */
.baseaddr = 0xF0000UL, /* 960KB */
.length = 0x10000UL, /* 64KB */
.type = E820_TYPE_RESERVED
},
{ /* lowmem */
.baseaddr = 0x100000UL, /* 1MB */
.length = 0x1ff00000UL, /* 511.0MB */
.type = E820_TYPE_RAM
},
{ /* between lowmem and PCI hole */
.baseaddr = 0x20000000UL, /* 512.0MB */
.length = 0xA0000000UL, /* 2560.0MB */
.type = E820_TYPE_RESERVED
},
{ /* between PCI hole and 4 GB */
.baseaddr = 0xe0000000UL, /* 3.5GB */
.length = 0x20000000UL, /* 512.0MB */
.type = E820_TYPE_RESERVED
},
};
/**
* @pre vm != NULL
*/
void create_prelaunched_vm_e820(struct acrn_vm *vm)
{
if (vm->vm_id == 0x0U)
{
vm->e820_entry_num = VM0_VE820_ENTRIES_WHL_IPC_I5;
vm->e820_entries = vm0_ve820_entry;
}
if (vm->vm_id == 0x1U)
{
vm->e820_entry_num = VM1_VE820_ENTRIES_WHL_IPC_I5;
vm->e820_entries = vm1_ve820_entry;
}
}

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hypervisor/arch/x86/configs/whl-ipc-i5/whl-ipc-i5_acpi_info.h Normal file
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/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* DO NOT MODIFY THIS FILE UNLESS YOU KNOW WHAT YOU ARE DOING!
*/
#ifndef PLATFORM_ACPI_INFO_H
#define PLATFORM_ACPI_INFO_H
/*
* BIOS Information
* Vendor: American Megatrends Inc.
* Version: WL10R104
* Release Date: 09/12/2019
* BIOS Revision: 5.13
*
* Base Board Information
* Manufacturer: Maxtang
* Product Name: WL10
* Version: V1.0
*/
/* pm sstate data */
#define PM1A_EVT_ADDRESS 0x1800UL
#define PM1A_EVT_ACCESS_SIZE 0x2U
#define PM1A_CNT_ADDRESS 0x1804UL
/* S3 is not supported by BIOS */
#undef S3_PKG_VAL_PM1A
#define S3_PKG_VAL_PM1A 0x0U
#define WAKE_VECTOR_32 0x8C8AA08CUL
#define WAKE_VECTOR_64 0x8C8AA098UL
#define RESET_REGISTER_ADDRESS 0xCF9UL
#define RESET_REGISTER_SPACE_ID SPACE_SYSTEM_IO
#define RESET_REGISTER_VALUE 0x6U
/* DRHD of DMAR */
#define DRHD_COUNT 2U
#define DRHD0_DEV_CNT 0x1U
#define DRHD0_SEGMENT 0x0U
#define DRHD0_FLAGS 0x0U
#define DRHD0_REG_BASE 0xFED90000UL
#define DRHD0_IGNORE true
#define DRHD0_DEVSCOPE0_TYPE 0x1U
#define DRHD0_DEVSCOPE0_ID 0x0U
#define DRHD0_DEVSCOPE0_BUS 0x0U
#define DRHD0_DEVSCOPE0_PATH 0x10U
#define DRHD1_DEV_CNT 0x2U
#define DRHD1_SEGMENT 0x0U
#define DRHD1_FLAGS 0x1U
#define DRHD1_REG_BASE 0xFED91000UL
#define DRHD1_IGNORE false
#define DRHD1_DEVSCOPE0_TYPE 0x3U
#define DRHD1_DEVSCOPE0_ID 0x2U
#define DRHD1_DEVSCOPE0_BUS 0x0U
#define DRHD1_DEVSCOPE0_PATH 0xf7U
#define DRHD1_DEVSCOPE1_TYPE 0x4U
#define DRHD1_DEVSCOPE1_ID 0x0U
#define DRHD1_DEVSCOPE1_BUS 0x0U
#define DRHD1_DEVSCOPE1_PATH 0xf6U
/* PCI mmcfg base of MCFG */
#define DEFAULT_PCI_MMCFG_BASE 0xe0000000UL
#endif /* PLATFORM_ACPI_INFO_H */