diff --git a/hypervisor/Makefile b/hypervisor/Makefile
index 6aab4095d..91fda5a5f 100644
--- a/hypervisor/Makefile
+++ b/hypervisor/Makefile
@@ -140,6 +140,8 @@ C_SRCS += arch/x86/configs/$(CONFIG_BOARD)/ve820.c
 C_SRCS += arch/x86/configs/$(CONFIG_BOARD)/pt_dev.c
 endif
 
+C_SRCS += arch/x86/configs/$(CONFIG_BOARD)/board.c
+
 C_SRCS += boot/acpi.c
 C_SRCS += boot/dmar_parse.c
 S_SRCS += arch/x86/idt.S
diff --git a/hypervisor/arch/x86/configs/apl-mrb/board.c b/hypervisor/arch/x86/configs/apl-mrb/board.c
new file mode 100644
index 000000000..830a75dcc
--- /dev/null
+++ b/hypervisor/arch/x86/configs/apl-mrb/board.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <board.h>
+
+struct platform_clos_info platform_clos_array[0];
+uint16_t platform_clos_num = 0;
diff --git a/hypervisor/arch/x86/configs/apl-up2/board.c b/hypervisor/arch/x86/configs/apl-up2/board.c
new file mode 100644
index 000000000..7102ca4d7
--- /dev/null
+++ b/hypervisor/arch/x86/configs/apl-up2/board.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <board.h>
+#include <msr.h>
+
+struct platform_clos_info platform_clos_array[4] = {
+	{
+		.clos_mask = 0xff,
+		.msr_index = MSR_IA32_L2_MASK_0,
+	},
+	{
+		.clos_mask = 0xff,
+		.msr_index = MSR_IA32_L2_MASK_1,
+	},
+	{
+		.clos_mask = 0xff,
+		.msr_index = MSR_IA32_L2_MASK_2,
+	},
+	{
+		.clos_mask = 0xff,
+		.msr_index = MSR_IA32_L2_MASK_3,
+	},
+};
+
+uint16_t platform_clos_num = (uint16_t)(sizeof(platform_clos_array)/sizeof(struct platform_clos_info));
diff --git a/hypervisor/arch/x86/configs/dnv-cb2/board.c b/hypervisor/arch/x86/configs/dnv-cb2/board.c
new file mode 100644
index 000000000..830a75dcc
--- /dev/null
+++ b/hypervisor/arch/x86/configs/dnv-cb2/board.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <board.h>
+
+struct platform_clos_info platform_clos_array[0];
+uint16_t platform_clos_num = 0;
diff --git a/hypervisor/arch/x86/configs/nuc6cayh/board.c b/hypervisor/arch/x86/configs/nuc6cayh/board.c
new file mode 100644
index 000000000..830a75dcc
--- /dev/null
+++ b/hypervisor/arch/x86/configs/nuc6cayh/board.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <board.h>
+
+struct platform_clos_info platform_clos_array[0];
+uint16_t platform_clos_num = 0;
diff --git a/hypervisor/arch/x86/configs/nuc7i7bnh/board.c b/hypervisor/arch/x86/configs/nuc7i7bnh/board.c
new file mode 100644
index 000000000..830a75dcc
--- /dev/null
+++ b/hypervisor/arch/x86/configs/nuc7i7bnh/board.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <board.h>
+
+struct platform_clos_info platform_clos_array[0];
+uint16_t platform_clos_num = 0;
diff --git a/hypervisor/include/arch/x86/board.h b/hypervisor/include/arch/x86/board.h
new file mode 100644
index 000000000..b38cee24e
--- /dev/null
+++ b/hypervisor/include/arch/x86/board.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2019 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef BOARD_H
+#define BOARD_H
+
+#include <types.h>
+
+struct platform_clos_info {
+	uint32_t clos_mask;
+	uint32_t msr_index;
+};
+
+extern struct platform_clos_info platform_clos_array[];
+extern uint16_t platform_clos_num;
+
+#endif /* BOARD_H */
diff --git a/hypervisor/include/arch/x86/msr.h b/hypervisor/include/arch/x86/msr.h
index 3d47320f8..1122c1fc3 100644
--- a/hypervisor/include/arch/x86/msr.h
+++ b/hypervisor/include/arch/x86/msr.h
@@ -341,6 +341,9 @@
 #define MSR_IA32_PM_CTL1			0x00000DB1U
 #define MSR_IA32_THREAD_STALL			0x00000DB2U
 #define MSR_IA32_L2_MASK_0			0x00000D10U
+#define MSR_IA32_L2_MASK_1			0x00000D11U
+#define MSR_IA32_L2_MASK_2			0x00000D12U
+#define MSR_IA32_L2_MASK_3			0x00000D13U
 #define MSR_IA32_BNDCFGS			0x00000D90U
 #define MSR_IA32_EFER				0xC0000080U
 #define MSR_IA32_STAR				0xC0000081U