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refine: change the address arguments type of mmio access api

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Change the address arguments type of mmio access api from uint64_t
to void*.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
This commit is contained in:
Zheng, Gen
2018-04-16 11:50:56 +08:00
committed by Jack Ren
parent 11d0e59b3e
commit d02f4d4a5f
5 changed files with 49 additions and 49 deletions
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10
hypervisor/arch/x86/interrupt.c
View File

@@ -215,11 +215,11 @@ void dump_lapic(void)
{
dev_dbg(ACRN_DBG_INTR,
"LAPIC: TIME %08x, init=0x%x cur=0x%x ISR=0x%x IRR=0x%x",
mmio_read_long(0xFEE00000 + LAPIC_LVT_TIMER_REGISTER),
mmio_read_long(0xFEE00000 + LAPIC_INITIAL_COUNT_REGISTER),
mmio_read_long(0xFEE00000 + LAPIC_CURRENT_COUNT_REGISTER),
mmio_read_long(0xFEE00000 + LAPIC_IN_SERVICE_REGISTER_7),
mmio_read_long(0xFEE00000 + LAPIC_INT_REQUEST_REGISTER_7));
mmio_read_long((void*)(0xFEE00000 + LAPIC_LVT_TIMER_REGISTER)),
mmio_read_long((void*)(0xFEE00000 + LAPIC_INITIAL_COUNT_REGISTER)),
mmio_read_long((void*)(0xFEE00000 + LAPIC_CURRENT_COUNT_REGISTER)),
mmio_read_long((void*)(0xFEE00000 + LAPIC_IN_SERVICE_REGISTER_7)),
mmio_read_long((void*)(0xFEE00000 + LAPIC_INT_REQUEST_REGISTER_7)));
}
int vcpu_inject_extint(struct vcpu *vcpu)

4
hypervisor/arch/x86/intr_lapic.c
View File

@@ -170,7 +170,7 @@ static inline uint32_t read_lapic_reg32(uint32_t offset)
if (offset < 0x20 || offset > 0x3ff)
return 0;
return mmio_read_long((uint64_t)lapic_info.xapic.vaddr + offset);
return mmio_read_long(lapic_info.xapic.vaddr + offset);
}
inline void write_lapic_reg32(uint32_t offset, uint32_t value)
@@ -178,7 +178,7 @@ inline void write_lapic_reg32(uint32_t offset, uint32_t value)
if (offset < 0x20 || offset > 0x3ff)
return;
mmio_write_long(value, (uint64_t)lapic_info.xapic.vaddr + offset);
mmio_write_long(value, lapic_info.xapic.vaddr + offset);
}
static void clear_lapic_isr(void)

14
hypervisor/arch/x86/vtd.c
View File

@@ -219,17 +219,17 @@ static int register_hrhd_units(void)
static uint32_t iommu_read32(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
{
return mmio_read_long(dmar_uint->drhd->reg_base_addr + offset);
return mmio_read_long((void*)(dmar_uint->drhd->reg_base_addr + offset));
}
static uint64_t iommu_read64(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
{
uint64_t value;
value = (mmio_read_long(dmar_uint->drhd->reg_base_addr + offset + 4));
value = (mmio_read_long((void*)(dmar_uint->drhd->reg_base_addr + offset + 4)));
value = value << 32;
value = value | (mmio_read_long(dmar_uint->drhd->reg_base_addr +
offset));
value = value | (mmio_read_long((void*)(dmar_uint->drhd->reg_base_addr +
offset)));
return value;
}
@@ -237,7 +237,7 @@ static uint64_t iommu_read64(struct dmar_drhd_rt *dmar_uint, uint32_t offset)
static void iommu_write32(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
uint32_t value)
{
mmio_write_long(value, dmar_uint->drhd->reg_base_addr + offset);
mmio_write_long(value, (void*)(dmar_uint->drhd->reg_base_addr + offset));
}
static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
@@ -246,10 +246,10 @@ static void iommu_write64(struct dmar_drhd_rt *dmar_uint, uint32_t offset,
uint32_t temp;
temp = value;
mmio_write_long(temp, dmar_uint->drhd->reg_base_addr + offset);
mmio_write_long(temp, (void*)(dmar_uint->drhd->reg_base_addr + offset));
temp = value >> 32;
mmio_write_long(temp, dmar_uint->drhd->reg_base_addr + offset + 4);
mmio_write_long(temp, (void*)(dmar_uint->drhd->reg_base_addr + offset + 4));
}
/* flush cache when root table, context table updated */