dm: add RTCT v2 support for guest

The latest version of RTCT specification is version 2.

 This patch is to add RTCT v2 support for virtual RTCT
 of guest.

Tracked-On: #6020
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Yonghua Huang
2021-05-27 09:14:33 +08:00
committed by wenlingz
parent 69808297b1
commit d0426fd249
3 changed files with 211 additions and 22 deletions

View File

@@ -17,6 +17,18 @@
#define RTCT_ENTRY_TYPE_RT_IOMMU 8U
#define RTCT_ENTRY_TYPE_MEM_HIERARCHY_LATENCY 9U
/*Entry IDs for RTCT version 2*/
#define RTCT_V2_COMPATIBILITY 0U
#define RTCT_V2_RTCD_LIMIT 1U
#define RTCT_V2_CRL_BINARY 2U
#define RTCT_V2_IA_WAYMASK 3U
#define RTCT_V2_WRC_WAYMASK 4U
#define RTCT_V2_GT_WAYMASK 5U
#define RTCT_V2_SSRAM_WAYMASK 6U
#define RTCT_V2_SSRAM 7U
#define RTCT_V2_MEMORY_HIERARCHY_LATENCY 8U
#define RTCT_V2_ERROR_LOG_ADDRESS 9U
struct rtct_entry {
uint16_t size;
uint16_t format_version;
@@ -24,6 +36,13 @@ struct rtct_entry {
uint32_t data[64];
} __packed;
struct rtct_entry_data_compatibility {
uint32_t RTCT_Ver_Major;
uint32_t RTCT_Ver_Minor;
uint32_t RTCD_Ver_Major;
uint32_t RTCD_Ver_Minor;
} __packed;
struct rtct_entry_data_ssram {
uint32_t cache_level;
uint64_t base;
@@ -32,6 +51,14 @@ struct rtct_entry_data_ssram {
uint32_t apic_id_tbl[64];
} __packed;
struct rtct_entry_data_ssram_v2 {
uint32_t cache_level;
uint32_t cache_id;
uint64_t base;
uint32_t size;
uint32_t shared;
} __packed;
struct rtct_entry_data_mem_hi_latency {
uint32_t hierarchy;
uint32_t clock_cycles;