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HV: Generalize RDT infrastructure and fix RDT

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cache configuration.

This patch creates a generic infrastructure for
RDT resources instead of just L2 or L3 cache. This
patch also fixes L3 CAT config overwrite by L2 in
cases where both L2 and L3 CAT are supported.

Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Vijay Dhanraj
2020-02-17 12:50:19 -08:00
committed by wenlingz
parent 887e3813bc
commit d0665fe220
6 changed files with 146 additions and 69 deletions
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10
hypervisor/arch/x86/cpu.c
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@@ -153,10 +153,10 @@ void init_pcpu_pre(bool is_bsp)
panic("System IOAPIC info is incorrect!");
}
#ifdef CONFIG_CAT_ENABLED
ret = init_cat_cap_info();
#ifdef CONFIG_RDT_ENABLED
ret = init_rdt_cap_info();
if (ret != 0) {
panic("Platform CAT info is incorrect!");
panic("Platform RDT info is incorrect!");
}
#endif
@@ -262,7 +262,9 @@ void init_pcpu_post(uint16_t pcpu_id)
init_sched(pcpu_id);
setup_clos(pcpu_id);
if (!setup_clos(pcpu_id)) {
panic("CLOS resource MSRs setup incorrectly!");
}
enable_smep();