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HV: Generalize RDT infrastructure and fix RDT

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cache configuration.

This patch creates a generic infrastructure for
RDT resources instead of just L2 or L3 cache. This
patch also fixes L3 CAT config overwrite by L2 in
cases where both L2 and L3 CAT are supported.

Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Vijay Dhanraj
2020-02-17 12:50:19 -08:00
committed by wenlingz
parent 887e3813bc
commit d0665fe220
6 changed files with 146 additions and 69 deletions
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2
hypervisor/include/arch/x86/cpufeatures.h
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@@ -74,7 +74,7 @@
#define X86_FEATURE_SMEP ((FEAT_7_0_EBX << 5U) + 7U)
#define X86_FEATURE_ERMS ((FEAT_7_0_EBX << 5U) + 9U)
#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5U) + 10U)
#define X86_FEATURE_CAT ((FEAT_7_0_EBX << 5U) + 15U)
#define X86_FEATURE_RDT_A ((FEAT_7_0_EBX << 5U) + 15U)
#define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5U) + 20U)
#define X86_FEATURE_CLFLUSHOPT ((FEAT_7_0_EBX << 5U) + 23U)

2
hypervisor/include/arch/x86/cpuid.h
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@@ -114,7 +114,7 @@
#define CPUID_SERIALNUM 3U
#define CPUID_EXTEND_FEATURE 7U
#define CPUID_XSAVE_FEATURES 0xDU
#define CPUID_RSD_ALLOCATION 0x10U
#define CPUID_RDT_ALLOCATION 0x10U
#define CPUID_MAX_EXTENDED_FUNCTION 0x80000000U
#define CPUID_EXTEND_FUNCTION_1 0x80000001U
#define CPUID_EXTEND_FUNCTION_2 0x80000002U

34
hypervisor/include/arch/x86/rdt.h
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@@ -7,26 +7,32 @@
#ifndef RDT_H
#define RDT_H
/* The intel Resource Director Tech(RDT) based Cache Allocation Tech support */
struct cat_hw_info {
bool enabled; /* If L2/L3 CAT enabled */
uint32_t bitmask; /* Used by other entities */
uint16_t cbm_len; /* Length of Cache mask in bits */
uint16_t clos_max; /* Maximum CLOS supported, the number of cache masks */
enum {
RDT_RESOURCE_L3,
RDT_RESOURCE_L2,
uint32_t res_id;
/* Must be the last */
RDT_NUM_RESOURCES,
};
extern struct cat_hw_info cat_cap_info;
#define RDT_RESID_L3 1U
#define RDT_RESID_L2 2U
extern const uint16_t hv_clos;
extern uint16_t platform_clos_num;
void setup_clos(uint16_t pcpu_id);
extern const uint16_t platform_clos_num;
/* The intel Resource Director Tech(RDT) based Allocation Tech support */
struct rdt_info {
uint32_t bitmask; /* Shared CLOS bitmask used by other entities */
uint16_t cbm_len; /* Length of Cache mask in bits */
uint16_t clos_max; /* Maximum CLOS supported, 0 indicates resource is not supported.*/
uint32_t res_id;
uint32_t msr_base; /* MSR base to program clos mask*/
struct platform_clos_info *platform_clos_array; /* user configured mask and MSR info for each CLOS*/
};
#define CAT_RESID_L3 1U
#define CAT_RESID_L2 2U
int32_t init_cat_cap_info(void);
int32_t init_rdt_cap_info(void);
bool setup_clos(uint16_t pcpu_id);
uint64_t clos2pqr_msr(uint16_t clos);
bool is_platform_rdt_capable(void);