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hv: emulate CR0.CD and CR0.NW

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This patch makes use of IA32_PAT MSR to emulate cache disabled behaviour

When the guest is requesting to set CR0.CD:
 - Keep guest's CR0.CD and CR0.NW bits unchanged
 - Write IA32_PAT MSR with all-UC entries to change the effective memory
   type for all GPA to UC for the guest VCPU
 - It depends on trapping wrmsr to IA32_PAT to prevent any entry in
   IA32_PAT being changed to non UC type by the guest

When the guest is requesting to clear CR0.CD:
 - restore the content of guest's IA32_PAT MSR

Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Zide Chen
2018-06-19 16:36:41 -07:00
committed by lijinxia
parent 6801d826e2
commit d0df39cbb5
3 changed files with 59 additions and 13 deletions
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18
hypervisor/include/arch/x86/msr.h
View File

@@ -519,6 +519,24 @@
/* 5 high-order bits in every field are reserved */
#define PAT_FIELD_RSV_BITS (0xF8U)
#define PAT_POWER_ON_VALUE (PAT_MEM_TYPE_WB + \
((uint64_t)PAT_MEM_TYPE_WT << 8) + \
((uint64_t)PAT_MEM_TYPE_UCM << 16) + \
((uint64_t)PAT_MEM_TYPE_UC << 24) + \
((uint64_t)PAT_MEM_TYPE_WB << 32) + \
((uint64_t)PAT_MEM_TYPE_WT << 40) + \
((uint64_t)PAT_MEM_TYPE_UCM << 48) + \
((uint64_t)PAT_MEM_TYPE_UC << 56))
#define PAT_ALL_UC_VALUE (PAT_MEM_TYPE_UC + \
((uint64_t)PAT_MEM_TYPE_UC << 8) + \
((uint64_t)PAT_MEM_TYPE_UC << 16) + \
((uint64_t)PAT_MEM_TYPE_UC << 24) + \
((uint64_t)PAT_MEM_TYPE_UC << 32) + \
((uint64_t)PAT_MEM_TYPE_UC << 40) + \
((uint64_t)PAT_MEM_TYPE_UC << 48) + \
((uint64_t)PAT_MEM_TYPE_UC << 56))
/* MTRR memory type definitions */
#define MTRR_MEM_TYPE_UC 0x00U /* uncached */
#define MTRR_MEM_TYPE_WC 0x01U /* write combining */

2
hypervisor/include/arch/x86/vmx.h
View File

@@ -391,7 +391,7 @@
#define RFLAGS_Z (1U<<6)
/* CR0 bits hv want to trap to track status change */
#define CR0_TRAP_MASK (CR0_PE | CR0_PG | CR0_WP)
#define CR0_TRAP_MASK (CR0_PE | CR0_PG | CR0_WP | CR0_CD | CR0_NW )
#define CR0_RESERVED_MASK ~(CR0_PG | CR0_CD | CR0_NW | CR0_AM | CR0_WP | \
CR0_NE | CR0_ET | CR0_TS | CR0_EM | CR0_MP | CR0_PE)