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hv: debug: Enable MMIO UART support

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New board, EHL CRB, does not have legacy port IO UART. Even the PCI UART
are not work due to BIOS's bug workaround(the BARs on LPSS PCI are reset
after BIOS hand over control to OS). For ACRN console usage, expose the
debug UART via ACPI PnP device (access by MMIO) and add support in
hypervisor debug code.

Another special thing is that register width of UART of EHL CRB is
1byte. Introduce reg_width for each struct console_uart.

Tracked-On: #4937
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
This commit is contained in:
Yin Fengwei
2020-08-20 13:23:39 +08:00
committed by wenlingz
parent 0c07999ec2
commit d0e06c4f80
4 changed files with 80 additions and 50 deletions
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12
hypervisor/arch/x86/Kconfig
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@@ -126,6 +126,11 @@ config SERIAL_LEGACY
Select this if the serial port shall be accessed via legacy port in/out
instructions.
config SERIAL_MMIO
bool "MMIO"
help
Select this if the serial port shall be accessed via MMIO registers.
endchoice
config SERIAL_PCI_BDF
@@ -144,6 +149,13 @@ config SERIAL_PIO_BASE
The base address of the serial ports. This is logically 16-bit but used
as a 64-bit integer.
config SERIAL_MMIO_BASE
hex "Base address of MMIO UART"
depends on SERIAL_MMIO
default 0xfe040000
help
The base address of the MMIO serial port.
config CONSOLE_LOGLEVEL_DEFAULT
int "Default loglevel on the serial console"
depends on !RELEASE