github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-09-23 09:47:44 +00:00
Code Issues Projects Releases Wiki Activity

hv: debug: Enable MMIO UART support

Browse Source 
New board, EHL CRB, does not have legacy port IO UART. Even the PCI UART
are not work due to BIOS's bug workaround(the BARs on LPSS PCI are reset
after BIOS hand over control to OS). For ACRN console usage, expose the
debug UART via ACPI PnP device (access by MMIO) and add support in
hypervisor debug code.

Another special thing is that register width of UART of EHL CRB is
1byte. Introduce reg_width for each struct console_uart.

Tracked-On: #4937
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
This commit is contained in:
Yin Fengwei
2020-08-20 13:23:39 +08:00
committed by wenlingz
parent 0c07999ec2
commit d0e06c4f80
4 changed files with 80 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
hypervisor/include/debug/uart16550.h
View File

@@ -127,10 +127,17 @@
/* UART oscillator clock */
#define UART_CLOCK_RATE 1843200U /* 1.8432 MHz */
enum serial_dev_type {
INVALID,
PIO,
PCI,
MMIO,
};
void uart16550_init(bool early_boot);
char uart16550_getc(void);
size_t uart16550_puts(const char *buf, uint32_t len);
void uart16550_set_property(bool enabled, bool port_mapped, uint64_t base_addr);
void uart16550_set_property(bool enabled, enum serial_dev_type uart_type, uint64_t base_addr);
bool is_pci_dbg_uart(union pci_bdf bdf_value);
#endif /* !UART16550_H */