diff --git a/hypervisor/arch/x86/guest/vmsr.c b/hypervisor/arch/x86/guest/vmsr.c
index 5618dd232..34250a819 100644
--- a/hypervisor/arch/x86/guest/vmsr.c
+++ b/hypervisor/arch/x86/guest/vmsr.c
@@ -78,7 +78,7 @@ static const uint32_t mtrr_msrs[NUM_MTRR_MSRS] = {
 };
 
 /* Following MSRs are intercepted, but it throws GPs for any guest accesses */
-#define NUM_UNSUPPORTED_MSRS	99U
+#define NUM_UNSUPPORTED_MSRS	104U
 static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
 	/* Variable MTRRs are not supported */
 	MSR_IA32_MTRR_PHYSBASE_0,
@@ -212,6 +212,13 @@ static const uint32_t unsupported_msrs[NUM_UNSUPPORTED_MSRS] = {
 	MSR_IA32_MCG_EXT_CTL,
 	/* MSR 0x280 ... 0x29F, not in this array */
 	/* MSR 0x400 ... 0x473, not in this array */
+
+	/* PRMRR related MSRs are configured by native BIOS / bootloader */
+	MSR_PRMRR_PHYS_BASE,
+	MSR_PRMRR_PHYS_MASK,
+	MSR_PRMRR_VALID_CONFIG,
+	MSR_UNCORE_PRMRR_PHYS_BASE,
+	MSR_UNCORE_PRMRR_PHYS_MASK,
 };
 
 /* emulated_guest_msrs[] shares same indexes with array vcpu->arch->guest_msrs[] */
diff --git a/hypervisor/include/arch/x86/msr.h b/hypervisor/include/arch/x86/msr.h
index c504c12b8..e953329e8 100644
--- a/hypervisor/include/arch/x86/msr.h
+++ b/hypervisor/include/arch/x86/msr.h
@@ -408,8 +408,13 @@
 #define MSR_LASTBRANCH_1			0x000001DCU
 #define MSR_LASTBRANCH_2			0x000001DDU
 #define MSR_LASTBRANCH_3			0x000001DEU
+#define MSR_PRMRR_PHYS_BASE			0x000001F4U
+#define MSR_PRMRR_PHYS_MASK			0x000001F5U
 #define MSR_PRMRR_VALID_CONFIG			0x000001FBU
 #define MSR_POWER_CTL				0x000001FCU
+#define MSR_UNCORE_PRMRR_PHYS_BASE		0x000002F4U
+#define MSR_UNCORE_PRMRR_PHYS_MASK		0x000002F5U
+
 #define MSR_BR_DETECT_CTRL			0x00000350U
 #define MSR_BR_DETECT_STATUS			0x00000351U
 #define MSR_UNCORE_PERF_GLOBAL_OVF_CTRL		0x00000393U