From d3b9712438c0ffb4c7d33157e71d4c8aa73ceb1c Mon Sep 17 00:00:00 2001 From: Xiangyang Wu Date: Mon, 16 Jul 2018 14:34:52 +0800 Subject: [PATCH] HV:INSTR:Rearrange register names in the enum cpu_reg_name In the current "enum cpu_reg_name", there are 16-bit segment register names, 16-bit descriptor table register names, and 16-bit task register names. These 16-bit register names are defined among the 64 bit register names. To access these 16-bit fields in VMCS and 32 bit fields in VMCS, more condition statements need to be used. Update 16-bit register names position to simplify conditions in vm_get_register and vm_set_register since different fields size accessing in VMCS by different vmread/vmwrite opreation. Note: After checking the current implementation, the register names of the same kind of registers (general registers, control registers, segment registers etc) need to be defined in order, some code checks the range by using this order. But different kinds of register names as group, this group position can be adjusted to simplify conditions. The follwoing register names group need to be considered in current implemetation: (1) General register names group: CPU_REG_RAX~CPU_REG_RDI; (2) Non-General register names group:CPU_REG_CR0~CPU_REG_LAST; (3) segment register names group:CPU_REG_ES~CPU_REG_GS. V1-->V2: This is new part of this patch serial created in V2 to rearrange register names as needed. V2--V3: Update comment information. V3-->V4: Define CPU_REG_NATURAL_LAST and CPU_REG_64BIT_LAST to make condition more understandable. Signed-off-by: Xiangyang Wu Reviewed-by: Junjie Mao --- .../arch/x86/guest/instr_emul_wrapper.h | 35 +++++++++++++++---- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/hypervisor/arch/x86/guest/instr_emul_wrapper.h b/hypervisor/arch/x86/guest/instr_emul_wrapper.h index 95d924005..7ff333369 100644 --- a/hypervisor/arch/x86/guest/instr_emul_wrapper.h +++ b/hypervisor/arch/x86/guest/instr_emul_wrapper.h @@ -31,8 +31,27 @@ #define INSTR_EMUL_WRAPPER_H #include -/* +/** + * * Identifiers for architecturally defined registers. + * + * These register names is used in condition statement. + * Within the following groups,register name need to be + * kept in order: + * General register names group (CPU_REG_RAX~CPU_REG_RDI); + * Non general register names group (CPU_REG_CR0~CPU_REG_LAST); + * Segement register names group (CPU_REG_ES~CPU_REG_GS). + * + * CPU_REG_NATURAL_LAST indicates in the non general register names + * group the register name (less than CPU_REG_NATURAL_last) is + * corresponds to the natural width field in VMCS; + * + * CPU_REG_64BIT_LAST indicates in the non general register names + * group the register name (less than CPU_REG_64BIT_LAST and more than + * CPU_REG_NATURAL_last) corresponds to the 64-bit field in VMCS. + * + * CPU_REG_LAST indicates the last register name. + * */ enum cpu_reg_name { CPU_REG_RAX, @@ -51,12 +70,20 @@ enum cpu_reg_name { CPU_REG_R15, CPU_REG_RDI, CPU_REG_CR0, + CPU_REG_CR2, CPU_REG_CR3, CPU_REG_CR4, CPU_REG_DR7, CPU_REG_RSP, CPU_REG_RIP, CPU_REG_RFLAGS, + CPU_REG_NATURAL_LAST, + CPU_REG_EFER, + CPU_REG_PDPTE0, + CPU_REG_PDPTE1, + CPU_REG_PDPTE2, + CPU_REG_PDPTE3, + CPU_REG_64BIT_LAST, CPU_REG_ES, CPU_REG_CS, CPU_REG_SS, @@ -67,12 +94,6 @@ enum cpu_reg_name { CPU_REG_TR, CPU_REG_IDTR, CPU_REG_GDTR, - CPU_REG_EFER, - CPU_REG_CR2, - CPU_REG_PDPTE0, - CPU_REG_PDPTE1, - CPU_REG_PDPTE2, - CPU_REG_PDPTE3, CPU_REG_LAST };