diff --git a/hypervisor/Makefile b/hypervisor/Makefile
index dd1948134..b9521c5c4 100644
--- a/hypervisor/Makefile
+++ b/hypervisor/Makefile
@@ -297,6 +297,7 @@ VP_DM_C_SRCS += dm/io_req.c
 VP_DM_C_SRCS += dm/vpci/vdev.c
 VP_DM_C_SRCS += dm/vpci/vpci.c
 VP_DM_C_SRCS += dm/vpci/vhostbridge.c
+VP_DM_C_SRCS += dm/vpci/vroot_port.c
 VP_DM_C_SRCS += dm/vpci/vpci_bridge.c
 VP_DM_C_SRCS += dm/vpci/ivshmem.c
 VP_DM_C_SRCS += dm/vpci/pci_pt.c
diff --git a/hypervisor/dm/vpci/vroot_port.c b/hypervisor/dm/vpci/vroot_port.c
new file mode 100644
index 000000000..5af7d7a69
--- /dev/null
+++ b/hypervisor/dm/vpci/vroot_port.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2021 Intel Corporation.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <pci.h>
+#include <asm/guest/vm.h>
+#include "vroot_port.h"
+
+#include "vpci_priv.h"
+
+#define PCIE_CAP_VPOS		0x40				/* pcie capability reg position */
+#define PTM_CAP_VPOS		PCI_ECAP_BASE_PTR	/* ptm capability reg postion */
+
+static void init_vroot_port(struct pci_vdev *vdev)
+{
+	/* vendor and device */
+	pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, VROOT_PORT_VENDOR);
+	pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, VROOT_PORT_DEVICE);
+
+	/* status register */
+	pci_vdev_write_vcfg(vdev, PCIR_STATUS, 2U, PCIM_STATUS_CAPPRESENT);
+
+	/* rev id */
+	pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, 0x01U);
+
+	/* sub class */
+	pci_vdev_write_vcfg(vdev, PCIR_SUBCLASS, 1U, PCIS_BRIDGE_PCI);
+
+	/* class */
+	pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, PCIC_BRIDGE);
+
+	/* Header Type */
+	pci_vdev_write_vcfg(vdev, PCIR_HDRTYPE, 1U, PCIM_HDRTYPE_BRIDGE);
+
+	/* capability pointer */
+	pci_vdev_write_vcfg(vdev, PCIR_CAP_PTR, 1U, PCIE_CAP_VPOS);
+
+	/* pcie capability registers */
+	pci_vdev_write_vcfg(vdev, PCIE_CAP_VPOS + PCICAP_ID, 1U, 0x10);
+	pci_vdev_write_vcfg(vdev, PCIE_CAP_VPOS + PCICAP_EXP_CAP, 2U, 0x0142);
+
+	vdev->parent_user = NULL;
+	vdev->user = vdev;
+}
+
+static void deinit_vroot_port(__unused struct pci_vdev *vdev)
+{
+	vdev->parent_user = NULL;
+	vdev->user = NULL;
+}
+
+static int32_t read_vroot_port_cfg(const struct pci_vdev *vdev, uint32_t offset,
+	uint32_t bytes, uint32_t *val)
+{
+	*val = pci_vdev_read_vcfg(vdev, offset, bytes);
+
+	return 0;
+}
+
+static int32_t write_vroot_port_cfg(__unused struct pci_vdev *vdev, __unused uint32_t offset,
+	__unused uint32_t bytes, __unused uint32_t val)
+{
+	pci_vdev_write_vcfg(vdev, offset, bytes, val);
+
+	return 0;
+}
+
+const struct pci_vdev_ops vroot_port_ops = {
+	.init_vdev         = init_vroot_port,
+	.deinit_vdev       = deinit_vroot_port,
+	.write_vdev_cfg    = write_vroot_port_cfg,
+	.read_vdev_cfg     = read_vroot_port_cfg,
+};
diff --git a/hypervisor/include/arch/x86/asm/vm_config.h b/hypervisor/include/arch/x86/asm/vm_config.h
index b143e413c..295452dcd 100644
--- a/hypervisor/include/arch/x86/asm/vm_config.h
+++ b/hypervisor/include/arch/x86/asm/vm_config.h
@@ -153,6 +153,7 @@ struct acrn_vm_pci_dev_config {
 	/* TODO: All device specific attributions need move to other place */
 	struct target_vuart t_vuart;
 	uint16_t vuart_idx;
+	uint16_t vroot_port_idx;
 	uint64_t vbar_base[PCI_BAR_COUNT];		/* vbar base address of PCI device, which is power-on default value */
 	struct pci_pdev *pdev;				/* the physical PCI device if it's a PT device */
 	const struct pci_vdev_ops *vdev_ops;		/* operations for PCI CFG read/write */
diff --git a/hypervisor/include/dm/vroot_port.h b/hypervisor/include/dm/vroot_port.h
new file mode 100644
index 000000000..f1155b3dc
--- /dev/null
+++ b/hypervisor/include/dm/vroot_port.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2021 Intel Corporation.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __VROOT_PORT_H
+#define __VROOT_PORT_H
+
+#include "vpci.h"
+
+#define VROOT_PORT_VENDOR			0x8086U
+#define VROOT_PORT_DEVICE			0x9d14U
+
+extern const struct pci_vdev_ops vroot_port_ops;
+
+#endif
diff --git a/hypervisor/include/hw/pci.h b/hypervisor/include/hw/pci.h
index 6f1bd12c2..5410aab28 100644
--- a/hypervisor/include/hw/pci.h
+++ b/hypervisor/include/hw/pci.h
@@ -109,6 +109,7 @@
 /* Capability Register Offsets */
 #define PCICAP_ID             0x0U
 #define PCICAP_NEXTPTR        0x1U
+#define PCICAP_EXP_CAP        0x2U
 
 /* Capability Identification Numbers */
 #define PCIY_MSI              0x05U