github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-08-13 22:06:49 +00:00
Code Issues Projects Releases Wiki Activity

config_tools: board_inspector: refactor ACPI RTCT parser

Browse Source 
This patch refactors and fixes the following in the ACPI RTCT parser of the
board inspector.

  1. Refactor to expose the RTCTSubtableSoftwareSRAM_v2 class directly as
     it is a fixed-size entry. There is no need to create a dynamic class
     which is mostly for variable-length entries.

  2. Rename the "format" field in RTCT entry header to "format_or_version",
     as that field actually means "version" in RTCT v2.

  3. Properly parse the RTCT compatibility entry which is currently parsed
     as an unknown entry with raw data.

Tracked-On: #7947
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao 2022-07-29 22:54:59 +08:00 committed by acrnsi-robot
parent 51e6dc5864
commit d7bac88e5e
1 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
misc/config_tools/board_inspector/acpiparser/rtct.py
View File

@ -15,7 +15,7 @@ class RTCTSubtable(cdata.Struct):
_pack_ = 1 _pack_ = 1
_fields_ = [ _fields_ = [
('subtable_size', ctypes.c_uint16), ('subtable_size', ctypes.c_uint16),
('format', ctypes.c_uint16), ('format_or_version', ctypes.c_uint16),
('type', ctypes.c_uint32), ('type', ctypes.c_uint32),
] ]
@ -152,17 +152,15 @@ class RTCTSubtableSSRAMWayMask(cdata.Struct):
('waymask', ctypes.c_uint32), ('waymask', ctypes.c_uint32),
] ]
def RTCTSubtableSoftwareSRAM_v2_factory(data_len): class RTCTSubtableSoftwareSRAM_v2(cdata.Struct):
class RTCTSubtableSoftwareSRAM_v2(cdata.Struct): _pack_ = 1
_pack_ = 1 _fields_ = copy.copy(RTCTSubtable._fields_) + [
_fields_ = copy.copy(RTCTSubtable._fields_) + [ ('level', ctypes.c_uint32),
('level', ctypes.c_uint32), ('cache_id', ctypes.c_uint32),
('cache_id', ctypes.c_uint32), ('base', ctypes.c_uint64),
('base', ctypes.c_uint64), ('size', ctypes.c_uint32),
('size', ctypes.c_uint32), ('shared', ctypes.c_uint32),
('shared', ctypes.c_uint32), ]
]
return RTCTSubtableSoftwareSRAM_v2
def RTCTSubtableMemoryHierarchyLatency_v2_factory(data_len): def RTCTSubtableMemoryHierarchyLatency_v2_factory(data_len):
class RTCTSubtableMemoryHierarchyLatency_v2(cdata.Struct): class RTCTSubtableMemoryHierarchyLatency_v2(cdata.Struct):
@ -226,7 +224,9 @@ def rtct_v2_subtable_list(addr, length):
subtable_num += 1 subtable_num += 1
subtable = RTCTSubtable.from_address(addr) subtable = RTCTSubtable.from_address(addr)
data_len = subtable.subtable_size - ctypes.sizeof(RTCTSubtable) data_len = subtable.subtable_size - ctypes.sizeof(RTCTSubtable)
if subtable.type == ACPI_RTCT_V2_TYPE_RTCD_Limits: if subtable.type == ACPI_RTCT_TYPE_COMPATIBILITY:
cls = RTCTSubtableCompatibility
elif subtable.type == ACPI_RTCT_V2_TYPE_RTCD_Limits:
cls = RTCTSubtableRTCDLimits cls = RTCTSubtableRTCDLimits
elif subtable.type == ACPI_RTCT_V2_TYPE_CRL_Binary: elif subtable.type == ACPI_RTCT_V2_TYPE_CRL_Binary:
cls = RTCTSubtableRTCMBinary cls = RTCTSubtableRTCMBinary
@ -239,7 +239,7 @@ def rtct_v2_subtable_list(addr, length):
elif subtable.type == ACPI_RTCT_V2_TYPE_SSRAM_WayMask: elif subtable.type == ACPI_RTCT_V2_TYPE_SSRAM_WayMask:
cls = RTCTSubtableSSRAMWayMask cls = RTCTSubtableSSRAMWayMask
elif subtable.type == ACPI_RTCT_V2_TYPE_SoftwareSRAM: elif subtable.type == ACPI_RTCT_V2_TYPE_SoftwareSRAM:
cls = RTCTSubtableSoftwareSRAM_v2_factory(data_len) cls = RTCTSubtableSoftwareSRAM_v2
elif subtable.type == ACPI_RTCT_V2_TYPE_MemoryHierarchyLatency: elif subtable.type == ACPI_RTCT_V2_TYPE_MemoryHierarchyLatency:
cls = RTCTSubtableMemoryHierarchyLatency_v2_factory(data_len) cls = RTCTSubtableMemoryHierarchyLatency_v2_factory(data_len)
elif subtable.type == ACPI_RTCT_V2_TYPE_ErrorLogAddress: elif subtable.type == ACPI_RTCT_V2_TYPE_ErrorLogAddress: