diff --git a/hypervisor/arch/x86/vtd.c b/hypervisor/arch/x86/vtd.c
index 782365a0c..cebfa7a93 100644
--- a/hypervisor/arch/x86/vtd.c
+++ b/hypervisor/arch/x86/vtd.c
@@ -10,8 +10,7 @@
 #include <errno.h>
 #include <asm/lib/bits.h>
 #include <asm/lib/spinlock.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
+#include <asm/cpu_caps.h>
 #include <irq.h>
 #include <asm/irq.h>
 #include <asm/io.h>
diff --git a/hypervisor/debug/uart16550.c b/hypervisor/debug/uart16550.c
index a00523c78..2509e4b37 100644
--- a/hypervisor/debug/uart16550.c
+++ b/hypervisor/debug/uart16550.c
@@ -7,9 +7,9 @@
 #include <types.h>
 #include <asm/lib/spinlock.h>
 #include <pci.h>
-#include <asm/pgtable.h>
 #include <uart16550.h>
 #include <asm/io.h>
+#include <asm/cpu.h>
 #include <asm/mmu.h>
 
 #define MAX_BDF_LEN 8
diff --git a/hypervisor/include/arch/x86/asm/cpu.h b/hypervisor/include/arch/x86/asm/cpu.h
index 1ee00f4bb..8e837be24 100644
--- a/hypervisor/include/arch/x86/asm/cpu.h
+++ b/hypervisor/include/arch/x86/asm/cpu.h
@@ -546,6 +546,26 @@ static inline void cpu_memory_barrier(void)
 	asm volatile ("mfence\n" : : : "memory");
 }
 
+static inline void invlpg(unsigned long addr)
+{
+	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
+}
+
+static inline void cache_flush_invalidate_all(void)
+{
+	asm volatile ("   wbinvd\n" : : : "memory");
+}
+
+static inline void clflush(const volatile void *p)
+{
+	asm volatile ("clflush (%0)" :: "r"(p));
+}
+
+static inline void clflushopt(const volatile void *p)
+{
+	asm volatile ("clflushopt (%0)" :: "r"(p));
+}
+
 /* Write the task register */
 #define CPU_LTR_EXECUTE(ltr_ptr)                            \
 {                                                           \
diff --git a/hypervisor/include/arch/x86/asm/mmu.h b/hypervisor/include/arch/x86/asm/mmu.h
index 86a8dcddb..e47875958 100644
--- a/hypervisor/include/arch/x86/asm/mmu.h
+++ b/hypervisor/include/arch/x86/asm/mmu.h
@@ -45,10 +45,8 @@
 
 #ifndef ASSEMBLER
 
-#include <asm/cpu.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/cpu_caps.h>
 
 /* Define cache line size (in bytes) */
 #define CACHE_LINE_SIZE		64U
@@ -196,26 +194,6 @@ void flush_address_space(void *addr, uint64_t size);
  */
 void invept(const void *eptp);
 
-static inline void invlpg(unsigned long addr)
-{
-	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
-}
-
-static inline void cache_flush_invalidate_all(void)
-{
-	asm volatile ("   wbinvd\n" : : : "memory");
-}
-
-static inline void clflush(const volatile void *p)
-{
-	asm volatile ("clflush (%0)" :: "r"(p));
-}
-
-static inline void clflushopt(const volatile void *p)
-{
-	asm volatile ("clflushopt (%0)" :: "r"(p));
-}
-
 /* get PDPT address from CR3 vaule in PAE mode */
 static inline uint64_t get_pae_pdpt_addr(uint64_t cr3)
 {