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https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-19 20:22:46 +00:00
hv: fix 'Function return value potentially unused'
MISRA-C requires that if the return value of a function call is assigned to a local variable, this value shall be used in all paths. This patch moves the variable assignment right before the moment that the variable is used. Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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@ -116,16 +116,14 @@ static void ptdev_build_physical_msi(struct acrn_vm *vm, struct ptdev_msi_info *
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}
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static union ioapic_rte
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ptdev_build_physical_rte(struct acrn_vm *vm,
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struct ptdev_remapping_info *entry)
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ptdev_build_physical_rte(struct acrn_vm *vm, struct ptdev_remapping_info *entry)
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{
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union ioapic_rte rte;
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uint32_t phys_irq = entry->allocated_pirq;
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uint32_t vector = irq_to_vector(phys_irq);
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union source_id *virt_sid = &entry->virt_sid;
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if (virt_sid->intx_id.src == PTDEV_VPIN_IOAPIC) {
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uint64_t vdmask, pdmask, delmode, dest_mask;
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uint64_t vdmask, pdmask, delmode, dest_mask, vector;
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uint32_t dest;
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union ioapic_rte virt_rte;
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bool phys;
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@ -164,9 +162,9 @@ ptdev_build_physical_rte(struct acrn_vm *vm,
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}
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/* update physical delivery mode, dest mode(logical) & vector */
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rte.full &= ~(IOAPIC_RTE_DESTMOD |
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IOAPIC_RTE_DELMOD | IOAPIC_RTE_INTVEC);
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rte.full |= IOAPIC_RTE_DESTLOG | delmode | (uint64_t)vector;
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vector = (uint64_t)irq_to_vector(phys_irq);
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rte.full &= ~(IOAPIC_RTE_DESTMOD | IOAPIC_RTE_DELMOD | IOAPIC_RTE_INTVEC);
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rte.full |= IOAPIC_RTE_DESTLOG | delmode | vector;
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dest_mask = calculate_logical_dest_mask(pdmask);
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/* update physical dest field */
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@ -899,7 +899,6 @@ static int get_gva_di_check(struct acrn_vcpu *vcpu, struct instr_emul_vie *vie,
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enum vm_cpu_mode cpu_mode;
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uint64_t val, gpa;
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val = vm_get_register(vcpu, CPU_REG_RDI);
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vm_get_seg_desc(CPU_REG_ES, &desc);
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cpu_mode = get_vcpu_mode(vcpu);
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@ -917,8 +916,8 @@ static int get_gva_di_check(struct acrn_vcpu *vcpu, struct instr_emul_vie *vie,
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}
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}
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if (vie_calculate_gla(cpu_mode, CPU_REG_ES, &desc, val, addrsize, gva)
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!= 0) {
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val = vm_get_register(vcpu, CPU_REG_RDI);
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if (vie_calculate_gla(cpu_mode, CPU_REG_ES, &desc, val, addrsize, gva) != 0) {
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goto exception_inject;
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}
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@ -664,7 +664,6 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
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lapic = &(vlapic->apic_page);
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lvtptr = vlapic_get_lvtptr(vlapic, offset);
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val = *lvtptr;
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idx = lvt_off_to_idx(offset);
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if ((lapic->svr.v & APIC_SVR_ENABLE) == 0U) {
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val |= APIC_LVT_M;
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@ -719,6 +718,7 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
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}
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*lvtptr = val;
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idx = lvt_off_to_idx(offset);
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atomic_store32(&vlapic->lvt_last[idx], val);
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}
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@ -64,11 +64,11 @@ static void create_secure_world_ept(struct acrn_vm *vm, uint64_t gpa_orig,
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uint64_t sworld_pml4e;
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uint64_t gpa;
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/* Check the HPA of parameter gpa_orig when invoking check_continuos_hpa */
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uint64_t hpa = gpa2hpa(vm, gpa_orig);
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uint64_t hpa;
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uint64_t table_present = EPT_RWX;
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uint64_t pdpte, *dest_pdpte_p, *src_pdpte_p;
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void *sub_table_addr, *pml4_base;
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struct acrn_vm *vm0 = get_vm_from_vmid(0U);
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struct acrn_vm *vm0;
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uint16_t i;
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if ((vm->sworld_control.flag.supported == 0UL)
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@ -86,9 +86,10 @@ static void create_secure_world_ept(struct acrn_vm *vm, uint64_t gpa_orig,
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return;
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}
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hpa = gpa2hpa(vm, gpa_orig);
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/* Unmap gpa_orig~gpa_orig+size from guest normal world ept mapping */
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ept_mr_del(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
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gpa_orig, size);
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ept_mr_del(vm, (uint64_t *)vm->arch_vm.nworld_eptp, gpa_orig, size);
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/* Copy PDPT entries from Normal world to Secure world
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* Secure world can access Normal World's memory,
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@ -105,7 +106,8 @@ static void create_secure_world_ept(struct acrn_vm *vm, uint64_t gpa_orig,
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/* The trusty memory is remapped to guest physical address
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* of gpa_rebased to gpa_rebased + size
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*/
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sub_table_addr = vm->arch_vm.ept_mem_ops.info->ept.sworld_pgtable_base + TRUSTY_PML4_PAGE_NUM(TRUSTY_EPT_REBASE_GPA);
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sub_table_addr = vm->arch_vm.ept_mem_ops.info->ept.sworld_pgtable_base +
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TRUSTY_PML4_PAGE_NUM(TRUSTY_EPT_REBASE_GPA);
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(void)memset(sub_table_addr, 0U, CPU_PAGE_SIZE);
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sworld_pml4e = hva2hpa(sub_table_addr) | table_present;
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set_pgentry((uint64_t *)pml4_base, sworld_pml4e);
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@ -128,29 +130,26 @@ static void create_secure_world_ept(struct acrn_vm *vm, uint64_t gpa_orig,
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dest_pdpte_p++;
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}
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/* Map [gpa_rebased, gpa_rebased + size) to secure ept mapping
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*/
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ept_mr_add(vm, (uint64_t *)vm->arch_vm.sworld_eptp,
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hpa, gpa_rebased, size, EPT_RWX | EPT_WB);
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/* Map [gpa_rebased, gpa_rebased + size) to secure ept mapping */
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ept_mr_add(vm, (uint64_t *)vm->arch_vm.sworld_eptp, hpa, gpa_rebased, size, EPT_RWX | EPT_WB);
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/* Get the gpa address in SOS */
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gpa = vm0_hpa2gpa(hpa);
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/* Unmap trusty memory space from sos ept mapping*/
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ept_mr_del(vm0, (uint64_t *)vm0->arch_vm.nworld_eptp,
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gpa, size);
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vm0 = get_vm_from_vmid(0U);
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ept_mr_del(vm0, (uint64_t *)vm0->arch_vm.nworld_eptp, gpa, size);
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/* Backup secure world info, will be used when
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* destroy secure world and suspend UOS */
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/* Backup secure world info, will be used when destroy secure world and suspend UOS */
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vm->sworld_control.sworld_memory.base_gpa_in_sos = gpa;
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vm->sworld_control.sworld_memory.base_gpa_in_uos = gpa_orig;
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vm->sworld_control.sworld_memory.base_hpa = hpa;
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vm->sworld_control.sworld_memory.length = size;
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}
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void destroy_secure_world(struct acrn_vm *vm, bool need_clr_mem)
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void destroy_secure_world(struct acrn_vm *vm, bool need_clr_mem)
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{
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struct acrn_vm *vm0 = get_vm_from_vmid(0U);
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struct acrn_vm *vm0;
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uint64_t hpa = vm->sworld_control.sworld_memory.base_hpa;
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uint64_t gpa_sos = vm->sworld_control.sworld_memory.base_gpa_in_sos;
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uint64_t gpa_uos = vm->sworld_control.sworld_memory.base_gpa_in_uos;
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@ -172,12 +171,11 @@ void destroy_secure_world(struct acrn_vm *vm, bool need_clr_mem)
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vm->arch_vm.sworld_eptp = NULL;
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/* restore memory to SOS ept mapping */
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ept_mr_add(vm0, vm0->arch_vm.nworld_eptp,
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hpa, gpa_sos, size, EPT_RWX | EPT_WB);
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vm0 = get_vm_from_vmid(0U);
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ept_mr_add(vm0, vm0->arch_vm.nworld_eptp, hpa, gpa_sos, size, EPT_RWX | EPT_WB);
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/* Restore memory to guest normal world */
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ept_mr_add(vm, vm->arch_vm.nworld_eptp,
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hpa, gpa_uos, size, EPT_RWX | EPT_WB);
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ept_mr_add(vm, vm->arch_vm.nworld_eptp, hpa, gpa_uos, size, EPT_RWX | EPT_WB);
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}
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@ -397,7 +397,7 @@ int acrn_handle_pending_request(struct acrn_vcpu *vcpu)
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uint32_t error_code;
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struct acrn_vcpu_arch * arch = &vcpu->arch;
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uint64_t *pending_req_bits = &arch->pending_req;
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struct acrn_vlapic *vlapic = vcpu_vlapic(vcpu);
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struct acrn_vlapic *vlapic;
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if (bitmap_test_and_clear_lock(ACRN_REQUEST_TRP_FAULT,
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pending_req_bits)) {
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@ -450,8 +450,8 @@ int acrn_handle_pending_request(struct acrn_vcpu *vcpu)
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* needed. And then try to handle vmcs event injection.
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*/
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if (is_apicv_intr_delivery_supported() &&
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bitmap_test_and_clear_lock(ACRN_REQUEST_EVENT,
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pending_req_bits)) {
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bitmap_test_and_clear_lock(ACRN_REQUEST_EVENT, pending_req_bits)) {
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vlapic = vcpu_vlapic(vcpu);
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vlapic_apicv_inject_pir(vlapic);
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}
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@ -365,7 +365,9 @@ static void dmar_enable_translation(struct dmar_drhd_rt *dmar_unit)
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iommu_write32(dmar_unit, DMAR_GCMD_REG, dmar_unit->gcmd);
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/* 32-bit register */
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dmar_wait_completion(dmar_unit, DMAR_GSTS_REG, DMA_GSTS_TES, false, &status);
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#if DBG_IOMMU
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status = iommu_read32(dmar_unit, DMAR_GSTS_REG);
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#endif
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}
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spinlock_release(&(dmar_unit->lock));
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