mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-26 15:31:35 +00:00
HV:refine 'apic_page' & 'pir_desc' in 'struct acrn_vlapic'
- update 'apic_page' field in 'struct acrn_vlapic', from pointer type to 'struct lapic_regs' type. - delete 'pir' and update 'pir_desc' to 'vlapic_pir_desc' type. - fix potential memory leak in 'vlapic_create()' should free allocated memory in case of registering mmio handler failure. Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Yonghua Huang
lijinxia
parent
17ef5076a4
commit
e0d40feaa8
@ -52,7 +52,7 @@
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static inline void vlapic_dump_irr(struct acrn_vlapic *vlapic, char *msg)
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{
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uint32_t i;
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struct lapic_reg *irrptr = &(vlapic)->apic_page->irr[0];
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struct lapic_reg *irrptr = &(vlapic->apic_page.irr[0]);
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for (i = 0U; i < 8U; i++)
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dev_dbg(ACRN_DBG_LAPIC, "%s irr%u 0x%08x",
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@ -62,7 +62,7 @@ static inline void vlapic_dump_irr(struct acrn_vlapic *vlapic, char *msg)
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static inline void vlapic_dump_isr(struct acrn_vlapic *vlapic, char *msg)
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{
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uint32_t i;
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struct lapic_reg *isrptr = &(vlapic)->apic_page->isr[0];
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struct lapic_reg *isrptr = &(vlapic->apic_page.isr[0]);
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for (i = 0U; i < 8U; i++) {
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dev_dbg(ACRN_DBG_LAPIC, "%s isr%u 0x%08x",
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@ -155,14 +155,14 @@ vm_active_cpus(struct vm *vm)
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uint32_t
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vlapic_get_id(struct acrn_vlapic *vlapic)
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{
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uint32_t id = vlapic->apic_page->id;
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uint32_t id = vlapic->apic_page.id;
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return id;
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}
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uint8_t
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vlapic_get_apicid(struct acrn_vlapic *vlapic)
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{
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uint32_t apicid = vlapic->apic_page->id >> APIC_ID_SHIFT;
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uint32_t apicid = (vlapic->apic_page.id) >> APIC_ID_SHIFT;
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return (uint8_t)apicid;
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}
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@ -192,7 +192,7 @@ vlapic_dfr_write_handler(struct acrn_vlapic *vlapic)
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{
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struct lapic_regs *lapic;
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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lapic->dfr &= APIC_DFR_MODEL_MASK;
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lapic->dfr |= APIC_DFR_RESERVED;
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@ -210,7 +210,7 @@ vlapic_ldr_write_handler(struct acrn_vlapic *vlapic)
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{
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struct lapic_regs *lapic;
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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lapic->ldr &= ~APIC_LDR_RESERVED;
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dev_dbg(ACRN_DBG_LAPIC, "vlapic LDR set to %#x", lapic->ldr);
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}
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@ -224,7 +224,7 @@ vlapic_id_write_handler(struct acrn_vlapic *vlapic)
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* We don't allow the ID register to be modified so reset it back to
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* its default value.
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*/
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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lapic->id = vlapic_get_id(vlapic);
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}
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@ -240,28 +240,29 @@ vlapic_timer_divisor_shift(uint32_t dcr)
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static inline bool
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vlapic_lvtt_oneshot(struct acrn_vlapic *vlapic)
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{
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return ((vlapic->apic_page->lvt[APIC_LVT_TIMER].val & APIC_LVTT_TM)
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return (((vlapic->apic_page.lvt[APIC_LVT_TIMER].val) & APIC_LVTT_TM)
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== APIC_LVTT_TM_ONE_SHOT);
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}
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static inline bool
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vlapic_lvtt_period(struct acrn_vlapic *vlapic)
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{
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return ((vlapic->apic_page->lvt[APIC_LVT_TIMER].val & APIC_LVTT_TM)
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return (((vlapic->apic_page.lvt[APIC_LVT_TIMER].val) & APIC_LVTT_TM)
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== APIC_LVTT_TM_PERIODIC);
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}
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static inline bool
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vlapic_lvtt_tsc_deadline(struct acrn_vlapic *vlapic)
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{
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return ((vlapic->apic_page->lvt[APIC_LVT_TIMER].val & APIC_LVTT_TM)
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return (((vlapic->apic_page.lvt[APIC_LVT_TIMER].val) & APIC_LVTT_TM)
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== APIC_LVTT_TM_TSCDLT);
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}
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static inline bool
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vlapic_lvtt_masked(struct acrn_vlapic *vlapic)
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{
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return (vlapic->apic_page->lvt[APIC_LVT_TIMER].val & APIC_LVTT_M) != 0U;
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return ((vlapic->apic_page.lvt[APIC_LVT_TIMER].val) & APIC_LVTT_M)
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!= 0U;
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}
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static void vlapic_create_timer(struct acrn_vlapic *vlapic)
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@ -372,7 +373,7 @@ static void vlapic_dcr_write_handler(struct acrn_vlapic *vlapic)
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{
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uint32_t divisor_shift;
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struct vlapic_timer *vtimer;
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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vtimer = &vlapic->vtimer;
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divisor_shift = vlapic_timer_divisor_shift(lapic->dcr_timer);
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@ -389,7 +390,7 @@ static void vlapic_icrtmr_write_handler(struct acrn_vlapic *vlapic)
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return;
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}
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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vtimer = &vlapic->vtimer;
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vtimer->tmicr = lapic->icr_timer;
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@ -448,7 +449,7 @@ vlapic_esr_write_handler(struct acrn_vlapic *vlapic)
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{
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struct lapic_regs *lapic;
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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lapic->esr = vlapic->esr_pending;
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vlapic->esr_pending = 0U;
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}
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@ -467,7 +468,7 @@ vlapic_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector, bool level)
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ASSERT(vector <= NR_MAX_VECTOR,
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"invalid vector %u", vector);
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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if ((lapic->svr & APIC_SVR_ENABLE) == 0U) {
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dev_dbg(ACRN_DBG_LAPIC,
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"vlapic is software disabled, ignoring interrupt %u",
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@ -557,7 +558,7 @@ lvt_off_to_idx(uint32_t offset)
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static inline uint32_t *
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vlapic_get_lvtptr(struct acrn_vlapic *vlapic, uint32_t offset)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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uint32_t i;
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switch (offset) {
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@ -592,7 +593,7 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
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uint32_t *lvtptr, mask, val, idx;
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struct lapic_regs *lapic;
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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lvtptr = vlapic_get_lvtptr(vlapic, offset);
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val = *lvtptr;
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idx = lvt_off_to_idx(offset);
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@ -656,7 +657,7 @@ vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
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static void
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vlapic_mask_lvts(struct acrn_vlapic *vlapic)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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lapic->lvt_cmci |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_CMCI_LVT);
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@ -722,7 +723,7 @@ dump_isrvec_stk(struct acrn_vlapic *vlapic)
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uint32_t i;
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struct lapic_reg *isrptr;
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isrptr = &vlapic->apic_page->isr[0];
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isrptr = &(vlapic->apic_page.isr[0]);
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for (i = 0U; i < 8U; i++) {
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printf("ISR%u 0x%08x\n", i, isrptr[i].val);
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}
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@ -749,7 +750,7 @@ vlapic_update_ppr(struct acrn_vlapic *vlapic)
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* bits is set in the ISRx registers.
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*/
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top_isrvec = (uint32_t)vlapic->isrvec_stk[vlapic->isrvec_stk_top];
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tpr = vlapic->apic_page->tpr;
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tpr = vlapic->apic_page.tpr;
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/* update ppr */
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{
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@ -782,7 +783,7 @@ vlapic_update_ppr(struct acrn_vlapic *vlapic)
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* corresponding entry on the isrvec stack.
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*/
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i = 1U;
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isrptr = &vlapic->apic_page->isr[0];
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isrptr = &(vlapic->apic_page.isr[0]);
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for (vector = 0U; vector < 256U; vector++) {
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idx = vector / 32U;
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if ((isrptr[idx].val & (1U << (vector % 32U))) != 0U) {
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@ -804,14 +805,14 @@ vlapic_update_ppr(struct acrn_vlapic *vlapic)
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ppr = top_isrvec & 0xf0U;
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}
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vlapic->apic_page->ppr = ppr;
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vlapic->apic_page.ppr = ppr;
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dev_dbg(ACRN_DBG_LAPIC, "%s 0x%02x", __func__, ppr);
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}
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static void
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vlapic_process_eoi(struct acrn_vlapic *vlapic)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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struct lapic_reg *isrptr, *tmrptr;
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uint32_t i, vector, bitpos;
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@ -979,8 +980,8 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
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bitmap_clear_lock(vcpu_id, &amask);
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vlapic = vm_lapic_from_vcpu_id(vm, vcpu_id);
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dfr = vlapic->apic_page->dfr;
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ldr = vlapic->apic_page->ldr;
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dfr = vlapic->apic_page.dfr;
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ldr = vlapic->apic_page.ldr;
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if ((dfr & APIC_DFR_MODEL_MASK) ==
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APIC_DFR_MODEL_FLAT) {
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@ -1012,8 +1013,8 @@ vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
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if (lowprio) {
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if (target == NULL) {
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target = vlapic;
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} else if (target->apic_page->ppr >
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vlapic->apic_page->ppr) {
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} else if (target->apic_page.ppr >
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vlapic->apic_page.ppr) {
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target = vlapic;
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} else {
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/* target is the dest */
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@ -1039,7 +1040,7 @@ calcvdest(struct vm *vm, uint64_t *dmask, uint32_t dest, bool phys)
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static void
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vlapic_set_tpr(struct acrn_vlapic *vlapic, uint32_t val)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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if (lapic->tpr != val) {
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dev_dbg(ACRN_DBG_LAPIC,
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@ -1052,7 +1053,7 @@ vlapic_set_tpr(struct acrn_vlapic *vlapic, uint32_t val)
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static uint32_t
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vlapic_get_tpr(struct acrn_vlapic *vlapic)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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return lapic->tpr;
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}
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@ -1093,7 +1094,7 @@ vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
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struct lapic_regs *lapic;
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struct vcpu *target_vcpu;
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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lapic->icr_lo &= ~APIC_DELSTAT_PEND;
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icr_low = lapic->icr_lo;
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@ -1213,7 +1214,7 @@ vlapic_icrlo_write_handler(struct acrn_vlapic *vlapic)
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int
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vlapic_pending_intr(struct acrn_vlapic *vlapic, uint32_t *vecptr)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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uint32_t i, vector, val, bitpos;
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struct lapic_reg *irrptr;
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@ -1245,7 +1246,7 @@ vlapic_pending_intr(struct acrn_vlapic *vlapic, uint32_t *vecptr)
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void
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vlapic_intr_accepted(struct acrn_vlapic *vlapic, uint32_t vector)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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struct lapic_reg *irrptr, *isrptr;
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uint32_t idx, stk_top;
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@ -1288,7 +1289,7 @@ vlapic_svr_write_handler(struct acrn_vlapic *vlapic)
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struct lapic_regs *lapic;
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uint32_t old, new, changed;
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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new = lapic->svr;
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old = vlapic->svr_last;
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@ -1334,7 +1335,7 @@ static int
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vlapic_read(struct acrn_vlapic *vlapic, uint32_t offset_arg,
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uint64_t *data)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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uint32_t i;
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uint32_t offset = offset_arg;
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@ -1458,7 +1459,7 @@ static int
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vlapic_write(struct acrn_vlapic *vlapic, uint32_t offset,
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uint64_t data)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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uint32_t *regptr;
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uint32_t data32 = (uint32_t)data;
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int retval;
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@ -1558,14 +1559,10 @@ vlapic_reset(struct acrn_vlapic *vlapic)
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{
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uint32_t i;
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struct lapic_regs *lapic;
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void *apic_page;
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lapic = vlapic->apic_page;
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apic_page = (void *)vlapic->apic_page;
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(void)memset(apic_page, 0U, CPU_PAGE_SIZE);
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if (vlapic->pir_desc) {
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(void)memset(vlapic->pir_desc, 0U, sizeof(struct vlapic_pir_desc));
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}
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lapic = &(vlapic->apic_page);
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(void)memset((void *)lapic, 0U, CPU_PAGE_SIZE);
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(void)memset((void *)&(vlapic->pir_desc), 0U, sizeof(vlapic->pir_desc));
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lapic->id = vlapic_build_id(vlapic);
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lapic->version = VLAPIC_VERSION;
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@ -1598,8 +1595,6 @@ vlapic_init(struct acrn_vlapic *vlapic)
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ASSERT(vlapic->vm != NULL, "%s: vm is not initialized", __func__);
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ASSERT(vlapic->vcpu->vcpu_id < phys_cpu_num,
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"%s: vcpu_id is not initialized", __func__);
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ASSERT(vlapic->apic_page != NULL,
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"%s: apic_page is not initialized", __func__);
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/*
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* If the vlapic is configured in x2apic mode then it will be
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@ -1621,7 +1616,7 @@ void vlapic_restore(struct acrn_vlapic *vlapic, struct lapic_regs *regs)
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struct lapic_regs *lapic;
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int i;
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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lapic->tpr = regs->tpr;
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lapic->apr = regs->apr;
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@ -1712,7 +1707,7 @@ vlapic_deliver_intr(struct vm *vm, bool level, uint32_t dest, bool phys,
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bool
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vlapic_enabled(struct acrn_vlapic *vlapic)
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{
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struct lapic_regs *lapic = vlapic->apic_page;
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struct lapic_regs *lapic = &(vlapic->apic_page);
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if (((vlapic->msr_apicbase & APICBASE_ENABLED) != 0U) &&
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((lapic->svr & APIC_SVR_ENABLE) != 0U)) {
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@ -1729,7 +1724,7 @@ vlapic_set_tmr(struct acrn_vlapic *vlapic, uint32_t vector, bool level)
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struct lapic_reg *tmrptr;
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uint32_t mask, idx;
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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tmrptr = &lapic->tmr[0];
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idx = vector / 32U;
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mask = 1U << (vector % 32U);
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@ -1902,7 +1897,7 @@ static void vlapic_timer_expired(void *data)
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struct lapic_regs *lapic;
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vlapic = vcpu->arch_vcpu.vlapic;
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lapic = vlapic->apic_page;
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lapic = &(vlapic->apic_page);
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/* inject vcpu timer interrupt if not masked */
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if (!vlapic_lvtt_masked(vlapic)) {
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@ -2046,17 +2041,11 @@ int vlapic_mmio_access_handler(struct vcpu *vcpu, struct io_request *io_req,
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int vlapic_create(struct vcpu *vcpu)
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{
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||||
void *apic_page = alloc_page();
|
||||
struct acrn_vlapic *vlapic = calloc(1U, sizeof(struct acrn_vlapic));
|
||||
|
||||
ASSERT(vlapic != NULL, "vlapic allocate failed");
|
||||
ASSERT(apic_page != NULL, "apic reg page allocate failed");
|
||||
|
||||
(void)memset((void *)apic_page, 0U, CPU_PAGE_SIZE);
|
||||
vlapic->vm = vcpu->vm;
|
||||
vlapic->vcpu = vcpu;
|
||||
vlapic->apic_page = (struct lapic_regs *)apic_page;
|
||||
|
||||
if (is_vapic_supported()) {
|
||||
if (is_vapic_intr_delivery_supported()) {
|
||||
vlapic->ops.apicv_set_intr_ready_fn =
|
||||
@ -2068,8 +2057,6 @@ int vlapic_create(struct vcpu *vcpu)
|
||||
vlapic->ops.apicv_set_tmr_fn = apicv_set_tmr;
|
||||
vlapic->ops.apicv_batch_set_tmr_fn =
|
||||
apicv_batch_set_tmr;
|
||||
|
||||
vlapic->pir_desc = (struct vlapic_pir_desc *)(&(vlapic->pir));
|
||||
}
|
||||
|
||||
if (is_vcpu_bsp(vcpu)) {
|
||||
@ -2087,6 +2074,7 @@ int vlapic_create(struct vcpu *vcpu)
|
||||
(uint64_t)DEFAULT_APIC_BASE +
|
||||
CPU_PAGE_SIZE,
|
||||
(void *) 0) != 0) {
|
||||
free(vlapic);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
@ -2100,7 +2088,6 @@ int vlapic_create(struct vcpu *vcpu)
|
||||
void vlapic_free(struct vcpu *vcpu)
|
||||
{
|
||||
struct acrn_vlapic *vlapic = NULL;
|
||||
void *apic_page = NULL;
|
||||
|
||||
if (vcpu == NULL) {
|
||||
return;
|
||||
@ -2119,13 +2106,6 @@ void vlapic_free(struct vcpu *vcpu)
|
||||
(uint64_t)DEFAULT_APIC_BASE + CPU_PAGE_SIZE);
|
||||
}
|
||||
|
||||
apic_page = vlapic->apic_page;
|
||||
if (apic_page == NULL) {
|
||||
free(vlapic);
|
||||
return;
|
||||
}
|
||||
|
||||
free(apic_page);
|
||||
free(vlapic);
|
||||
}
|
||||
|
||||
@ -2141,7 +2121,7 @@ apicv_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector,
|
||||
uint32_t idx;
|
||||
int32_t notify;
|
||||
|
||||
pir_desc = vlapic->pir_desc;
|
||||
pir_desc = &(vlapic->pir_desc);
|
||||
|
||||
idx = vector / 64U;
|
||||
mask = 1UL << (vector % 64U);
|
||||
@ -2159,14 +2139,14 @@ apicv_pending_intr(struct acrn_vlapic *vlapic, __unused uint32_t *vecptr)
|
||||
uint64_t pending, pirval;
|
||||
uint32_t i, ppr, vpr;
|
||||
|
||||
pir_desc = vlapic->pir_desc;
|
||||
pir_desc = &(vlapic->pir_desc);
|
||||
|
||||
pending = atomic_load64(&pir_desc->pending);
|
||||
if (pending == 0U) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
lapic = vlapic->apic_page;
|
||||
lapic = &(vlapic->apic_page);
|
||||
ppr = lapic->ppr & 0xF0U;
|
||||
|
||||
if (ppr == 0U) {
|
||||
@ -2211,7 +2191,7 @@ apicv_set_tmr(__unused struct acrn_vlapic *vlapic, uint32_t vector, bool level)
|
||||
static void
|
||||
apicv_batch_set_tmr(struct acrn_vlapic *vlapic)
|
||||
{
|
||||
struct lapic_regs *lapic = vlapic->apic_page;
|
||||
struct lapic_regs *lapic = &(vlapic->apic_page);
|
||||
uint64_t val;
|
||||
struct lapic_reg *ptr;
|
||||
uint32_t s, e;
|
||||
@ -2252,7 +2232,7 @@ apicv_get_apic_access_addr(__unused struct vm *vm)
|
||||
uint64_t
|
||||
apicv_get_apic_page_addr(struct acrn_vlapic *vlapic)
|
||||
{
|
||||
return HVA2HPA(vlapic->apic_page);
|
||||
return HVA2HPA(&(vlapic->apic_page));
|
||||
}
|
||||
|
||||
/*
|
||||
@ -2270,13 +2250,13 @@ apicv_inject_pir(struct acrn_vlapic *vlapic)
|
||||
uint16_t intr_status_old, intr_status_new;
|
||||
struct lapic_reg *irr = NULL;
|
||||
|
||||
pir_desc = vlapic->pir_desc;
|
||||
pir_desc = &(vlapic->pir_desc);
|
||||
if (atomic_cmpxchg64(&pir_desc->pending, 1UL, 0UL) != 1UL) {
|
||||
return;
|
||||
}
|
||||
|
||||
pirval = 0UL;
|
||||
lapic = vlapic->apic_page;
|
||||
lapic = &(vlapic->apic_page);
|
||||
irr = &lapic->irr[0];
|
||||
|
||||
for (i = 0U; i < 4U; i++) {
|
||||
@ -2382,7 +2362,7 @@ int veoi_vmexit_handler(struct vcpu *vcpu)
|
||||
vcpu_retain_rip(vcpu);
|
||||
|
||||
vlapic = vcpu->arch_vcpu.vlapic;
|
||||
lapic = vlapic->apic_page;
|
||||
lapic = &(vlapic->apic_page);
|
||||
vector = (uint32_t)(vcpu->arch_vcpu.exit_qualification & 0xFFUL);
|
||||
|
||||
tmrptr = &lapic->tmr[0];
|
||||
|
||||
@ -115,10 +115,18 @@ struct vlapic_timer {
|
||||
};
|
||||
|
||||
struct acrn_vlapic {
|
||||
/*
|
||||
* Please keep 'apic_page' and 'pir_desc' be the first two fields in
|
||||
* current structure, as below alignment restrictions are mandatory
|
||||
* to support APICv features:
|
||||
* - 'apic_page' MUST be 4KB aligned.
|
||||
* - 'pir_desc' MUST be 64 bytes aligned.
|
||||
*/
|
||||
struct lapic_regs apic_page;
|
||||
struct vlapic_pir_desc pir_desc;
|
||||
|
||||
struct vm *vm;
|
||||
struct vcpu *vcpu;
|
||||
struct lapic_regs *apic_page;
|
||||
struct vlapic_pir_desc *pir_desc;
|
||||
struct vlapic_ops ops;
|
||||
|
||||
uint32_t esr_pending;
|
||||
@ -153,7 +161,6 @@ struct acrn_vlapic {
|
||||
*/
|
||||
uint32_t svr_last;
|
||||
uint32_t lvt_last[VLAPIC_MAXLVT_INDEX + 1];
|
||||
struct vlapic_pir_desc pir;
|
||||
};
|
||||
} __aligned(CPU_PAGE_SIZE);
|
||||
|
||||
#endif /* _VLAPIC_PRIV_H_ */
|
||||
|
||||
@ -167,7 +167,7 @@ struct lapic_regs {
|
||||
/* reserved */ PAD4;
|
||||
uint32_t dcr_timer; PAD3;
|
||||
/* reserved */ PAD4;
|
||||
};
|
||||
} __aligned(CPU_PAGE_SIZE);
|
||||
|
||||
enum LAPIC_REGISTERS {
|
||||
LAPIC_ID = 0x2,
|
||||
|
||||
@ -233,6 +233,10 @@ static void deallocate_mem(struct mem_pool *pool, void *ptr)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The return address will be CPU_PAGE_SIZE aligned if 'num_bytes' is greater
|
||||
* than CPU_PAGE_SIZE.
|
||||
*/
|
||||
void *malloc(unsigned int num_bytes)
|
||||
{
|
||||
void *memory = NULL;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user