From e19d36fa6cbd9514e01aef6a12a927f19c7f89f2 Mon Sep 17 00:00:00 2001 From: Jason Chen CJ Date: Sun, 12 Aug 2018 20:47:04 +0800 Subject: [PATCH] change pcpu_sync_sleep to wait_sync_change pcpu_sync_sleep monitor "uint64_t sync" change to "1UL << mask_bit", which is not very clear to take use of it. change it to wait_sync_change, means monitor "uint64_t sync" change to "wake_sync", make the function clear to use. And expose it for the usage of the following patches. Signed-off-by: Jason Chen CJ --- hypervisor/arch/x86/cpu.c | 16 +++++++++------- hypervisor/include/arch/x86/cpu.h | 5 +++-- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/hypervisor/arch/x86/cpu.c b/hypervisor/arch/x86/cpu.c index bec82a833..fabaa9e85 100644 --- a/hypervisor/arch/x86/cpu.c +++ b/hypervisor/arch/x86/cpu.c @@ -485,9 +485,6 @@ static void bsp_boot_post(void) /* Start all secondary cores */ start_cpus(); - /* Trigger event to allow secondary CPUs to continue */ - bitmap_set_nolock(0U, &pcpu_sync); - ASSERT(get_cpu_id() == BOOT_CPU_ID, ""); init_iommu(); @@ -562,7 +559,7 @@ static void cpu_secondary_post(void) timer_init(); /* Wait for boot processor to signal all secondary cores to continue */ - pcpu_sync_sleep(&pcpu_sync, 0UL); + wait_sync_change(&pcpu_sync, 0UL); exec_vmxon_instr(get_cpu_id()); @@ -600,6 +597,9 @@ void start_cpus(void) uint16_t expected_up; uint64_t startup_paddr; + /* secondary cpu start up will wait for pcpu_sync -> 0UL */ + atomic_store64(&pcpu_sync, 1UL); + startup_paddr = prepare_trampoline(); /* Set flag showing number of CPUs expected to be up to all @@ -635,6 +635,9 @@ void start_cpus(void) do { } while (1); } + + /* Trigger event to allow secondary CPUs to continue */ + atomic_store64(&pcpu_sync, 0UL); } void stop_cpus(void) @@ -724,10 +727,9 @@ static void print_hv_banner(void) printf(boot_msg); } -static void pcpu_sync_sleep(uint64_t *sync, uint64_t mask_bit) +/* wait until *sync == wake_sync */ +void wait_sync_change(uint64_t *sync, uint64_t wake_sync) { - uint64_t wake_sync = (1UL << mask_bit); - if (get_monitor_cap()) { /* Wait for the event to be set using monitor/mwait */ asm volatile ("1: cmpq %%rbx,(%%rax)\n" diff --git a/hypervisor/include/arch/x86/cpu.h b/hypervisor/include/arch/x86/cpu.h index 63ba8b7ed..9c695e905 100644 --- a/hypervisor/include/arch/x86/cpu.h +++ b/hypervisor/include/arch/x86/cpu.h @@ -331,8 +331,9 @@ bool cpu_has_cap(uint32_t bit); void load_cpu_state_data(void); void bsp_boot_init(void); void cpu_secondary_init(void); -void start_cpus(void); -void stop_cpus(void); +void start_cpus(); +void stop_cpus(); +void wait_sync_change(uint64_t *sync, uint64_t wake_sync); /* Read control register */ #define CPU_CR_READ(cr, result_ptr) \