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hv: assign: fix MISRA-C violations on implicit type conversion

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This patch fixes the MISRA-C violations in arch/x86/assign.c
on implicit type conversion.

Tracked-On: #861
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Binbin Wu 2018-12-18 20:50:23 +08:00 committed by wenlingz
parent 714814f97e
commit e19dcf5735
1 changed files with 10 additions and 15 deletions
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25
hypervisor/arch/x86/assign.c
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@ -132,7 +132,7 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
union ioapic_rte virt_rte; union ioapic_rte virt_rte;
bool phys; bool phys;
vioapic_get_rte(vm, virt_sid->intx_id.pin, &virt_rte); vioapic_get_rte(vm, (uint32_t)virt_sid->intx_id.pin, &virt_rte);
rte = virt_rte; rte = virt_rte;
/* init polarity & pin state */ /* init polarity & pin state */
@ -185,7 +185,7 @@ ptirq_build_physical_rte(struct acrn_vm *vm, struct ptirq_remapping_info *entry)
/* just update trigger mode */ /* just update trigger mode */
ioapic_get_rte(phys_irq, &phys_rte); ioapic_get_rte(phys_irq, &phys_rte);
rte.full = phys_rte.full & (~IOAPIC_RTE_TRGRMOD); rte.full = phys_rte.full & (~IOAPIC_RTE_TRGRMOD);
vpic_get_irq_trigger(vm, virt_sid->intx_id.pin, &trigger); vpic_get_irq_trigger(vm, (uint32_t)virt_sid->intx_id.pin, &trigger);
if (trigger == LEVEL_TRIGGER) { if (trigger == LEVEL_TRIGGER) {
rte.full |= IOAPIC_RTE_TRGRLVL; rte.full |= IOAPIC_RTE_TRGRLVL;
} }
@ -396,26 +396,22 @@ static void ptirq_handle_intx(struct acrn_vm *vm,
bool trigger_lvl = false; bool trigger_lvl = false;
/* VPIN_IOAPIC src means we have vioapic enabled */ /* VPIN_IOAPIC src means we have vioapic enabled */
vioapic_get_rte(vm, virt_sid->intx_id.pin, &rte); vioapic_get_rte(vm, (uint32_t)virt_sid->intx_id.pin, &rte);
if ((rte.full & IOAPIC_RTE_TRGRMOD) == IOAPIC_RTE_TRGRLVL) { if ((rte.full & IOAPIC_RTE_TRGRMOD) == IOAPIC_RTE_TRGRLVL) {
trigger_lvl = true; trigger_lvl = true;
} }
if (trigger_lvl) { if (trigger_lvl) {
if (entry->polarity != 0U) { if (entry->polarity != 0U) {
vioapic_set_irq(vm, virt_sid->intx_id.pin, vioapic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_LOW);
GSI_SET_LOW);
} else { } else {
vioapic_set_irq(vm, virt_sid->intx_id.pin, vioapic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_HIGH);
GSI_SET_HIGH);
} }
} else { } else {
if (entry->polarity != 0U) { if (entry->polarity != 0U) {
vioapic_set_irq(vm, virt_sid->intx_id.pin, vioapic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_FALLING_PULSE);
GSI_FALLING_PULSE);
} else { } else {
vioapic_set_irq(vm, virt_sid->intx_id.pin, vioapic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_RAISING_PULSE);
GSI_RAISING_PULSE);
} }
} }
@ -431,12 +427,11 @@ static void ptirq_handle_intx(struct acrn_vm *vm,
enum vpic_trigger trigger; enum vpic_trigger trigger;
/* VPIN_PIC src means we have vpic enabled */ /* VPIN_PIC src means we have vpic enabled */
vpic_get_irq_trigger(vm, virt_sid->intx_id.pin, &trigger); vpic_get_irq_trigger(vm, (uint32_t)virt_sid->intx_id.pin, &trigger);
if (trigger == LEVEL_TRIGGER) { if (trigger == LEVEL_TRIGGER) {
vpic_set_irq(vm, virt_sid->intx_id.pin, GSI_SET_HIGH); vpic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_SET_HIGH);
} else { } else {
vpic_set_irq(vm, virt_sid->intx_id.pin, vpic_set_irq(vm, (uint32_t)virt_sid->intx_id.pin, GSI_RAISING_PULSE);
GSI_RAISING_PULSE);
} }
break; break;
} }