HV: enable acpi pm1a register info fixup

Previously ACPI PM1A register info was hardcoded to 0 in HV for generic boards,
but SOS still can know the real PM1A info so the system would hang if user
trigger S3 in SOS. Enabling PM1A register info fixup will let HV be able to
intercept the operation on PM1A and then make basic function of S3 work for
all boards;

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Victor Sun
2019-04-29 13:52:37 +08:00
committed by wenlingz
parent 81e13de407
commit e2d723d4fa
8 changed files with 77 additions and 46 deletions

View File

@@ -12,8 +12,6 @@
#ifndef PLATFORM_ACPI_INFO_H
#define PLATFORM_ACPI_INFO_H
#define ACPI_INFO_VALIDATED
/* pm sstate data */
#define PM1A_EVT_ACCESS_SIZE 3U
#define PM1A_EVT_ADDRESS 0x400UL

View File

@@ -100,15 +100,19 @@ void vm_setup_cpu_state(struct acrn_vm *vm)
*/
int32_t vm_load_pm_s_state(struct acrn_vm *vm)
{
#ifdef ACPI_INFO_VALIDATED
vm->pm.sx_state_data = get_host_sstate_data();
pr_info("System S3/S5 is supported.");
return 0;
#else
vm->pm.sx_state_data = NULL;
pr_err("System S3/S5 is NOT supported.");
return -1;
#endif
int32_t ret;
struct pm_s_state_data *sx_data = get_host_sstate_data();
if ((sx_data->pm1a_evt.address == 0UL) || (sx_data->pm1a_cnt.address == 0UL)
|| (sx_data->wake_vector_32 == NULL)) {
pr_err("System S3/S5 is NOT supported.");
ret = -1;
} else {
pr_info("System S3/S5 is supported.");
vm->pm.sx_state_data = sx_data;
ret = 0;
}
return ret;
}
static inline uint32_t s3_enabled(uint32_t pm1_cnt)

View File

@@ -65,12 +65,6 @@ static struct pm_s_state_data host_pm_s_state = {
.wake_vector_64 = (uint64_t *)WAKE_VECTOR_64
};
void set_host_wake_vectors(void *vector_32, void *vector_64)
{
host_pm_s_state.wake_vector_32 = (uint32_t *)vector_32;
host_pm_s_state.wake_vector_64 = (uint64_t *)vector_64;
}
struct pm_s_state_data *get_host_sstate_data(void)
{
return &host_pm_s_state;