mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-21 05:02:24 +00:00
hv: refine 'uint64_t' string print format in x86 moudle
Use "0x%lx" string to format 'uint64_t' type value, instead of "0x%llx". Tracked-On: #4020 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
This commit is contained in:
Yonghua Huang
wenlingz
parent
fb29d1f99f
commit
e51386fe04
@ -151,7 +151,7 @@ void init_e820(void)
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hv_e820[i].type = mmap[i].type;
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dev_dbg(ACRN_DBG_E820, "mmap table: %d type: 0x%x\n", i, mmap[i].type);
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dev_dbg(ACRN_DBG_E820, "Base: 0x%016llx length: 0x%016llx",
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dev_dbg(ACRN_DBG_E820, "Base: 0x%016lx length: 0x%016lx",
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mmap[i].baseaddr, mmap[i].length);
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}
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}
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@ -160,7 +160,7 @@ static void ptirq_build_physical_msi(struct acrn_vm *vm, struct ptirq_msi_info *
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info->pmsi_addr.bits.rh = MSI_ADDR_RH;
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info->pmsi_addr.bits.dest_mode = MSI_ADDR_DESTMODE_LOGICAL;
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}
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dev_dbg(ACRN_DBG_IRQ, "MSI %s addr:data = 0x%llx:%x(V) -> 0x%llx:%x(P)",
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dev_dbg(ACRN_DBG_IRQ, "MSI %s addr:data = 0x%lx:%x(V) -> 0x%lx:%x(P)",
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(info->pmsi_addr.ir_bits.intr_format != 0U) ? " Remappable Format" : "Compatibility Format",
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info->vmsi_addr.full, info->vmsi_data.full,
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info->pmsi_addr.full, info->pmsi_data.full);
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@ -548,7 +548,7 @@ void ptirq_softirq(uint16_t pcpu_id)
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entry->allocated_pirq,
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msi->vmsi_data.bits.vector,
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irq_to_vector(entry->allocated_pirq));
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dev_dbg(ACRN_DBG_PTIRQ, " vmsi_addr: 0x%llx vmsi_data: 0x%x",
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dev_dbg(ACRN_DBG_PTIRQ, " vmsi_addr: 0x%lx vmsi_data: 0x%x",
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msi->vmsi_addr.full,
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msi->vmsi_data.full);
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}
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@ -93,10 +93,10 @@ int32_t ept_misconfig_vmexit_handler(__unused struct acrn_vcpu *vcpu)
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status = -EINVAL;
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/* TODO - EPT Violation handler */
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pr_fatal("%s, Guest linear address: 0x%016llx ",
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pr_fatal("%s, Guest linear address: 0x%016lx ",
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__func__, exec_vmread(VMX_GUEST_LINEAR_ADDR));
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pr_fatal("%s, Guest physical address: 0x%016llx ",
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pr_fatal("%s, Guest physical address: 0x%016lx ",
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__func__, exec_vmread64(VMX_GUEST_PHYSICAL_ADDR_FULL));
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ASSERT(status == 0, "EPT Misconfiguration is not handled.\n");
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@ -113,7 +113,7 @@ void ept_add_mr(struct acrn_vm *vm, uint64_t *pml4_page,
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struct acrn_vcpu *vcpu;
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uint64_t prot = prot_orig;
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dev_dbg(ACRN_DBG_EPT, "%s, vm[%d] hpa: 0x%016llx gpa: 0x%016llx size: 0x%016llx prot: 0x%016x\n",
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dev_dbg(ACRN_DBG_EPT, "%s, vm[%d] hpa: 0x%016lx gpa: 0x%016lx size: 0x%016lx prot: 0x%016x\n",
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__func__, vm->vm_id, hpa, gpa, size, prot);
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/* EPT & VT-d share the same page tables, set SNP bit
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@ -139,7 +139,7 @@ void ept_modify_mr(struct acrn_vm *vm, uint64_t *pml4_page,
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uint16_t i;
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uint64_t local_prot = prot_set;
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dev_dbg(ACRN_DBG_EPT, "%s,vm[%d] gpa 0x%llx size 0x%llx\n", __func__, vm->vm_id, gpa, size);
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dev_dbg(ACRN_DBG_EPT, "%s,vm[%d] gpa 0x%lx size 0x%lx\n", __func__, vm->vm_id, gpa, size);
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if (((local_prot & EPT_MT_MASK) != EPT_UNCACHED) && iommu_snoop_supported(vm->iommu)) {
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local_prot |= EPT_SNOOP_CTRL;
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@ -159,7 +159,7 @@ void ept_del_mr(struct acrn_vm *vm, uint64_t *pml4_page, uint64_t gpa, uint64_t
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struct acrn_vcpu *vcpu;
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uint16_t i;
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dev_dbg(ACRN_DBG_EPT, "%s,vm[%d] gpa 0x%llx size 0x%llx\n", __func__, vm->vm_id, gpa, size);
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dev_dbg(ACRN_DBG_EPT, "%s,vm[%d] gpa 0x%lx size 0x%lx\n", __func__, vm->vm_id, gpa, size);
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mmu_modify_or_del(pml4_page, gpa, size, 0UL, 0UL, &vm->arch_vm.ept_mem_ops, MR_DEL);
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@ -315,7 +315,7 @@ static inline uint32_t local_copy_gpa(struct acrn_vm *vm, void *h_ptr, uint64_t
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hpa = local_gpa2hpa(vm, gpa, &pg_size);
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if (hpa == INVALID_HPA) {
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pr_err("%s,vm[%hu] gpa 0x%llx,GPA is unmapping",
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pr_err("%s,vm[%hu] gpa 0x%lx,GPA is unmapping",
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__func__, vm->vm_id, gpa);
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len = 0U;
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} else {
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@ -188,7 +188,7 @@ hyperv_wrmsr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t wval)
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break;
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}
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dev_dbg(ACRN_DBG_HYPERV, "hv: %s: MSR=0x%x wval=0x%llx vcpuid=%d vmid=%d",
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dev_dbg(ACRN_DBG_HYPERV, "hv: %s: MSR=0x%x wval=0x%lx vcpuid=%d vmid=%d",
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__func__, msr, wval, vcpu->vcpu_id, vcpu->vm->vm_id);
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return ret;
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@ -221,7 +221,7 @@ hyperv_rdmsr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *rval)
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break;
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}
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dev_dbg(ACRN_DBG_HYPERV, "hv: %s: MSR=0x%x rval=0x%llx vcpuid=%d vmid=%d",
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dev_dbg(ACRN_DBG_HYPERV, "hv: %s: MSR=0x%x rval=0x%lx vcpuid=%d vmid=%d",
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__func__, msr, *rval, vcpu->vcpu_id, vcpu->vm->vm_id);
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return ret;
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@ -2355,7 +2355,7 @@ int32_t decode_instruction(struct acrn_vcpu *vcpu)
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retval = vie_init(&emul_ctxt->vie, vcpu);
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if (retval < 0) {
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if (retval != -EFAULT) {
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pr_err("init vie failed @ 0x%016llx:", vcpu_get_rip(vcpu));
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pr_err("init vie failed @ 0x%016lx:", vcpu_get_rip(vcpu));
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}
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} else {
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@ -2365,7 +2365,7 @@ int32_t decode_instruction(struct acrn_vcpu *vcpu)
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retval = local_decode_instruction(cpu_mode, seg_desc_def32(csar), &emul_ctxt->vie);
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if (retval != 0) {
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pr_err("decode instruction failed @ 0x%016llx:", vcpu_get_rip(vcpu));
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pr_err("decode instruction failed @ 0x%016lx:", vcpu_get_rip(vcpu));
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vcpu_inject_ud(vcpu);
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retval = -EFAULT;
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} else {
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@ -235,7 +235,7 @@ static void vmx_write_cr0(struct acrn_vcpu *vcpu, uint64_t cr0)
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/* clear read cache, next time read should from VMCS */
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bitmap_clear_lock(CPU_REG_CR0, &vcpu->reg_cached);
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pr_dbg("VMM: Try to write %016llx, allow to write 0x%016llx to CR0", cr0_mask, cr0_vmx);
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pr_dbg("VMM: Try to write %016lx, allow to write 0x%016lx to CR0", cr0_mask, cr0_vmx);
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}
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}
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}
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@ -337,7 +337,7 @@ static void vmx_write_cr4(struct acrn_vcpu *vcpu, uint64_t cr4)
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/* clear read cache, next time read should from VMCS */
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bitmap_clear_lock(CPU_REG_CR4, &vcpu->reg_cached);
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pr_dbg("VMM: Try to write %016llx, allow to write 0x%016llx to CR4", cr4, cr4_vmx);
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pr_dbg("VMM: Try to write %016lx, allow to write 0x%016lx to CR4", cr4, cr4_vmx);
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}
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}
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}
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@ -388,12 +388,12 @@ void init_cr0_cr4_host_mask(void)
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exec_vmwrite(VMX_CR0_GUEST_HOST_MASK, cr0_host_owned_bits);
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/* Output CR0 mask value */
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pr_dbg("CR0 guest-host mask value: 0x%016llx", cr0_host_owned_bits);
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pr_dbg("CR0 guest-host mask value: 0x%016lx", cr0_host_owned_bits);
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exec_vmwrite(VMX_CR4_GUEST_HOST_MASK, cr4_host_owned_bits);
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/* Output CR4 mask value */
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pr_dbg("CR4 guest-host mask value: 0x%016llx", cr4_host_owned_bits);
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pr_dbg("CR4 guest-host mask value: 0x%016lx", cr4_host_owned_bits);
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}
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uint64_t vcpu_get_cr0(struct acrn_vcpu *vcpu)
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@ -1130,7 +1130,7 @@ vlapic_calc_dest_lapic_pt(struct acrn_vm *vm, uint64_t *dmask, bool is_broadcast
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}
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bitmap_set_nolock(vcpu_id, dmask);
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}
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dev_dbg(ACRN_DBG_LAPICPT, "%s: logical destmod, dmask: 0x%016llx", __func__, *dmask);
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dev_dbg(ACRN_DBG_LAPICPT, "%s: logical destmod, dmask: 0x%016lx", __func__, *dmask);
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}
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}
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@ -1527,7 +1527,7 @@ static int32_t vlapic_read(struct acrn_vlapic *vlapic, uint32_t offset_arg, uint
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}
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}
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dev_dbg(ACRN_DBG_LAPIC, "vlapic read offset %#x, data %#llx", offset, *data);
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dev_dbg(ACRN_DBG_LAPIC, "vlapic read offset %x, data %lx", offset, *data);
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return ret;
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}
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@ -334,7 +334,7 @@ static void prepare_sos_vm_memmap(struct acrn_vm *vm)
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const struct e820_entry *p_e820 = vm->e820_entries;
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const struct mem_range *p_mem_range_info = get_mem_range_info();
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pr_dbg("sos_vm: bottom memory - 0x%llx, top memory - 0x%llx\n",
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pr_dbg("sos_vm: bottom memory - 0x%lx, top memory - 0x%lx\n",
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p_mem_range_info->mem_bottom, p_mem_range_info->mem_top);
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if (p_mem_range_info->mem_top > EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE)) {
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@ -357,7 +357,7 @@ static void prepare_sos_vm_memmap(struct acrn_vm *vm)
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for (i = 0U; i < entries_count; i++) {
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entry = p_e820 + i;
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pr_dbg("e820 table: %d type: 0x%x", i, entry->type);
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pr_dbg("BaseAddress: 0x%016llx length: 0x%016llx\n", entry->baseaddr, entry->length);
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pr_dbg("BaseAddress: 0x%016lx length: 0x%016lx\n", entry->baseaddr, entry->length);
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}
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/* Unmap all platform EPC resource from SOS.
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@ -609,7 +609,7 @@ int32_t shutdown_vm(struct acrn_vm *vm)
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wait_pcpus_offline(mask);
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if ((mask != 0UL) && (!start_pcpus(mask))) {
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pr_fatal("Failed to start all cpus in mask(0x%llx)", mask);
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pr_fatal("Failed to start all cpus in mask(0x%lx)", mask);
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ret = -ETIMEDOUT;
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}
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@ -690,7 +690,7 @@ int32_t reset_vm(struct acrn_vm *vm)
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wait_pcpus_offline(mask);
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if ((mask != 0UL) && (!start_pcpus(mask))) {
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pr_fatal("Failed to start all cpus in mask(0x%llx)", mask);
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pr_fatal("Failed to start all cpus in mask(0x%lx)", mask);
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ret = -ETIMEDOUT;
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}
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@ -227,7 +227,7 @@ int32_t vmcall_vmexit_handler(struct acrn_vcpu *vcpu)
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uint64_t hypcall_id = vcpu_get_gpreg(vcpu, CPU_REG_R8);
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if (!is_hypercall_from_ring0()) {
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pr_err("hypercall 0x%llx is only allowed from RING-0!\n", hypcall_id);
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pr_err("hypercall 0x%lx is only allowed from RING-0!\n", hypcall_id);
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vcpu_inject_gp(vcpu, 0U);
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ret = -EACCES;
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} else if (hypcall_id == HC_WORLD_SWITCH) {
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@ -243,7 +243,7 @@ int32_t vmcall_vmexit_handler(struct acrn_vcpu *vcpu)
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/* Dispatch the hypercall handler */
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ret = dispatch_sos_hypercall(vcpu);
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} else {
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pr_err("hypercall 0x%llx is only allowed from SOS_VM!\n", hypcall_id);
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pr_err("hypercall 0x%lx is only allowed from SOS_VM!\n", hypcall_id);
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vcpu_inject_ud(vcpu);
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ret = -ENODEV;
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}
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@ -31,14 +31,14 @@ static void init_guest_vmx(struct acrn_vcpu *vcpu, uint64_t cr0, uint64_t cr3,
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exec_vmwrite(VMX_GUEST_CR3, cr3);
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exec_vmwrite(VMX_GUEST_GDTR_BASE, ectx->gdtr.base);
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pr_dbg("VMX_GUEST_GDTR_BASE: 0x%016llx", ectx->gdtr.base);
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pr_dbg("VMX_GUEST_GDTR_BASE: 0x%016lx", ectx->gdtr.base);
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exec_vmwrite32(VMX_GUEST_GDTR_LIMIT, ectx->gdtr.limit);
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pr_dbg("VMX_GUEST_GDTR_LIMIT: 0x%016llx", ectx->gdtr.limit);
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pr_dbg("VMX_GUEST_GDTR_LIMIT: 0x%016lx", ectx->gdtr.limit);
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exec_vmwrite(VMX_GUEST_IDTR_BASE, ectx->idtr.base);
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pr_dbg("VMX_GUEST_IDTR_BASE: 0x%016llx", ectx->idtr.base);
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pr_dbg("VMX_GUEST_IDTR_BASE: 0x%016lx", ectx->idtr.base);
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exec_vmwrite32(VMX_GUEST_IDTR_LIMIT, ectx->idtr.limit);
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pr_dbg("VMX_GUEST_IDTR_LIMIT: 0x%016llx", ectx->idtr.limit);
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pr_dbg("VMX_GUEST_IDTR_LIMIT: 0x%016lx", ectx->idtr.limit);
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/* init segment selectors: es, cs, ss, ds, fs, gs, ldtr, tr */
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load_segment(ectx->cs, VMX_GUEST_CS);
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@ -143,7 +143,7 @@ static void init_host_state(void)
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tss_addr = hva2hpa((void *)&get_cpu_var(tss));
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/* Set up host TR base fields */
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exec_vmwrite(VMX_HOST_TR_BASE, tss_addr);
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pr_dbg("VMX_HOST_TR_BASE: 0x%016llx ", tss_addr);
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pr_dbg("VMX_HOST_TR_BASE: 0x%016lx ", tss_addr);
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/* Obtain the current interrupt descriptor table base */
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idt_base = sidt();
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@ -161,11 +161,11 @@ static void init_host_state(void)
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value64 = msr_read(MSR_IA32_PAT);
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exec_vmwrite64(VMX_HOST_IA32_PAT_FULL, value64);
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pr_dbg("VMX_HOST_IA32_PAT: 0x%016llx ", value64);
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pr_dbg("VMX_HOST_IA32_PAT: 0x%016lx ", value64);
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value64 = msr_read(MSR_IA32_EFER);
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exec_vmwrite64(VMX_HOST_IA32_EFER_FULL, value64);
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pr_dbg("VMX_HOST_IA32_EFER: 0x%016llx ",
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pr_dbg("VMX_HOST_IA32_EFER: 0x%016lx ",
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value64);
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/**************************************************/
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@ -174,31 +174,31 @@ static void init_host_state(void)
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/* Set up host CR0 field */
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CPU_CR_READ(cr0, &value);
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exec_vmwrite(VMX_HOST_CR0, value);
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pr_dbg("VMX_HOST_CR0: 0x%016llx ", value);
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pr_dbg("VMX_HOST_CR0: 0x%016lx ", value);
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/* Set up host CR3 field */
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CPU_CR_READ(cr3, &value);
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exec_vmwrite(VMX_HOST_CR3, value);
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pr_dbg("VMX_HOST_CR3: 0x%016llx ", value);
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pr_dbg("VMX_HOST_CR3: 0x%016lx ", value);
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/* Set up host CR4 field */
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CPU_CR_READ(cr4, &value);
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exec_vmwrite(VMX_HOST_CR4, value);
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pr_dbg("VMX_HOST_CR4: 0x%016llx ", value);
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pr_dbg("VMX_HOST_CR4: 0x%016lx ", value);
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/* Set up host and guest FS base address */
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value = msr_read(MSR_IA32_FS_BASE);
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exec_vmwrite(VMX_HOST_FS_BASE, value);
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pr_dbg("VMX_HOST_FS_BASE: 0x%016llx ", value);
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pr_dbg("VMX_HOST_FS_BASE: 0x%016lx ", value);
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value = msr_read(MSR_IA32_GS_BASE);
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exec_vmwrite(VMX_HOST_GS_BASE, value);
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pr_dbg("VMX_HOST_GS_BASE: 0x%016llx ", value);
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pr_dbg("VMX_HOST_GS_BASE: 0x%016lx ", value);
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/* Set up host instruction pointer on VM Exit */
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value64 = (uint64_t)&vm_exit;
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pr_dbg("HOST RIP on VMExit %016llx ", value64);
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pr_dbg("HOST RIP on VMExit %016lx ", value64);
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exec_vmwrite(VMX_HOST_RIP, value64);
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pr_dbg("vm exit return address = %016llx ", value64);
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pr_dbg("vm exit return address = %016lx ", value64);
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/* As a type I hypervisor, just init sysenter fields to 0 */
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exec_vmwrite32(VMX_HOST_IA32_SYSENTER_CS, 0U);
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@ -353,7 +353,7 @@ static void init_exec_ctrl(struct acrn_vcpu *vcpu)
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*/
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value64 = hva2hpa(vm->arch_vm.nworld_eptp) | (3UL << 3U) | 6UL;
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exec_vmwrite64(VMX_EPT_POINTER_FULL, value64);
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pr_dbg("VMX_EPT_POINTER: 0x%016llx ", value64);
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pr_dbg("VMX_EPT_POINTER: 0x%016lx ", value64);
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/* Set up guest exception mask bitmap setting a bit * causes a VM exit
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* on corresponding guest * exception - pg 2902 24.6.3
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@ -384,10 +384,10 @@ static void init_exec_ctrl(struct acrn_vcpu *vcpu)
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/* Set up IO bitmap register A and B - pg 2902 24.6.4 */
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value64 = hva2hpa(vm->arch_vm.io_bitmap);
|
||||
exec_vmwrite64(VMX_IO_BITMAP_A_FULL, value64);
|
||||
pr_dbg("VMX_IO_BITMAP_A: 0x%016llx ", value64);
|
||||
pr_dbg("VMX_IO_BITMAP_A: 0x%016lx ", value64);
|
||||
value64 = hva2hpa((void *)&(vm->arch_vm.io_bitmap[PAGE_SIZE]));
|
||||
exec_vmwrite64(VMX_IO_BITMAP_B_FULL, value64);
|
||||
pr_dbg("VMX_IO_BITMAP_B: 0x%016llx ", value64);
|
||||
pr_dbg("VMX_IO_BITMAP_B: 0x%016lx ", value64);
|
||||
|
||||
init_msr_emulation(vcpu);
|
||||
|
||||
|
||||
@ -205,11 +205,11 @@ int32_t vmexit_handler(struct acrn_vcpu *vcpu)
|
||||
basic_exit_reason = (uint16_t)(vcpu->arch.exit_reason & 0xFFFFU);
|
||||
|
||||
/* Log details for exit */
|
||||
pr_dbg("Exit Reason: 0x%016llx ", vcpu->arch.exit_reason);
|
||||
pr_dbg("Exit Reason: 0x%016lx ", vcpu->arch.exit_reason);
|
||||
|
||||
/* Ensure exit reason is within dispatch table */
|
||||
if (basic_exit_reason >= ARRAY_SIZE(dispatch_table)) {
|
||||
pr_err("Invalid Exit Reason: 0x%016llx ", vcpu->arch.exit_reason);
|
||||
pr_err("Invalid Exit Reason: 0x%016lx ", vcpu->arch.exit_reason);
|
||||
ret = -EINVAL;
|
||||
} else {
|
||||
/* Calculate dispatch table entry */
|
||||
@ -244,12 +244,12 @@ int32_t vmexit_handler(struct acrn_vcpu *vcpu)
|
||||
|
||||
static int32_t unhandled_vmexit_handler(struct acrn_vcpu *vcpu)
|
||||
{
|
||||
pr_fatal("Error: Unhandled VM exit condition from guest at 0x%016llx ",
|
||||
pr_fatal("Error: Unhandled VM exit condition from guest at 0x%016lx ",
|
||||
exec_vmread(VMX_GUEST_RIP));
|
||||
|
||||
pr_fatal("Exit Reason: 0x%016llx ", vcpu->arch.exit_reason);
|
||||
pr_fatal("Exit Reason: 0x%016lx ", vcpu->arch.exit_reason);
|
||||
|
||||
pr_err("Exit qualification: 0x%016llx ",
|
||||
pr_err("Exit qualification: 0x%016lx ",
|
||||
exec_vmread(VMX_EXIT_QUALIFICATION));
|
||||
|
||||
TRACE_2L(TRACE_VMEXIT_UNHANDLED, vcpu->arch.exit_reason, 0UL);
|
||||
@ -259,7 +259,7 @@ static int32_t unhandled_vmexit_handler(struct acrn_vcpu *vcpu)
|
||||
|
||||
static int32_t triple_fault_vmexit_handler(struct acrn_vcpu *vcpu)
|
||||
{
|
||||
pr_fatal("VM%d: triple fault @ guest RIP 0x%016llx, exit qualification: 0x%016llx",
|
||||
pr_fatal("VM%d: triple fault @ guest RIP 0x%016lx, exit qualification: 0x%016lx",
|
||||
vcpu->vm->vm_id, exec_vmread(VMX_GUEST_RIP), exec_vmread(VMX_EXIT_QUALIFICATION));
|
||||
triple_fault_shutdown_vm(vcpu);
|
||||
|
||||
|
||||
@ -347,7 +347,7 @@ void init_msr_emulation(struct acrn_vcpu *vcpu)
|
||||
/* Setup MSR bitmap - Intel SDM Vol3 24.6.9 */
|
||||
value64 = hva2hpa(vcpu->arch.msr_bitmap);
|
||||
exec_vmwrite64(VMX_MSR_BITMAP_FULL, value64);
|
||||
pr_dbg("VMX_MSR_BITMAP: 0x%016llx ", value64);
|
||||
pr_dbg("VMX_MSR_BITMAP: 0x%016lx ", value64);
|
||||
|
||||
/* Initialize the MSR save/store area */
|
||||
init_msr_area(vcpu);
|
||||
@ -362,7 +362,7 @@ static int32_t write_pat_msr(struct acrn_vcpu *vcpu, uint64_t value)
|
||||
for (i = 0U; i < 8U; i++) {
|
||||
field = (value >> (i * 8U)) & 0xffUL;
|
||||
if (pat_mem_type_invalid(field) || ((PAT_FIELD_RSV_BITS & field) != 0UL)) {
|
||||
pr_err("invalid guest IA32_PAT: 0x%016llx", value);
|
||||
pr_err("invalid guest IA32_PAT: 0x%016lx", value);
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -127,7 +127,7 @@ void init_vmtrr(struct acrn_vcpu *vcpu)
|
||||
vmtrr->fixed_range[i].value = MTRR_FIXED_RANGE_ALL_WB;
|
||||
}
|
||||
|
||||
pr_dbg("vm%d vcpu%hu fixed-range MTRR[%u]: %16llx",
|
||||
pr_dbg("vm%d vcpu%hu fixed-range MTRR[%u]: %16lx",
|
||||
vcpu->vm->vm_id, vcpu->vcpu_id, i,
|
||||
vmtrr->fixed_range[i].value);
|
||||
}
|
||||
|
||||
@ -164,8 +164,8 @@ int32_t ept_violation_vmexit_handler(struct acrn_vcpu *vcpu)
|
||||
}
|
||||
|
||||
if (ret <= 0) {
|
||||
pr_acrnlog("Guest Linear Address: 0x%016llx", exec_vmread(VMX_GUEST_LINEAR_ADDR));
|
||||
pr_acrnlog("Guest Physical Address address: 0x%016llx", gpa);
|
||||
pr_acrnlog("Guest Linear Address: 0x%016lx", exec_vmread(VMX_GUEST_LINEAR_ADDR));
|
||||
pr_acrnlog("Guest Physical Address address: 0x%016lx", gpa);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
@ -106,7 +106,7 @@ static inline int32_t asm_invept(uint64_t type, struct invept_desc desc)
|
||||
static inline void local_invept(uint64_t type, struct invept_desc desc)
|
||||
{
|
||||
if (asm_invept(type, desc) != 0) {
|
||||
pr_dbg("%s, failed. type = %llu, eptp = 0x%llx", __func__, type, desc.eptp);
|
||||
pr_dbg("%s, failed. type = %llu, eptp = 0x%lx", __func__, type, desc.eptp);
|
||||
}
|
||||
}
|
||||
|
||||
@ -228,7 +228,7 @@ void init_paging(void)
|
||||
high64_max_ram = round_pde_up(p_mem_range_info->mem_top);
|
||||
if ((high64_max_ram > (CONFIG_PLATFORM_RAM_SIZE + PLATFORM_LO_MMIO_SIZE)) ||
|
||||
(high64_max_ram < (1UL << 32U))) {
|
||||
printf("ERROR!!! high64_max_ram: 0x%llx, top address space: 0x%llx\n",
|
||||
printf("ERROR!!! high64_max_ram: 0x%lx, top address space: 0x%lx\n",
|
||||
high64_max_ram, CONFIG_PLATFORM_RAM_SIZE + PLATFORM_LO_MMIO_SIZE);
|
||||
panic("Please configure HV_ADDRESS_SPACE correctly!\n");
|
||||
}
|
||||
|
||||
@ -41,7 +41,7 @@ static void split_large_page(uint64_t *pte, enum _page_table_level level,
|
||||
break;
|
||||
}
|
||||
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, paddr: 0x%llx, pbase: 0x%llx\n", __func__, ref_paddr, pbase);
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, paddr: 0x%lx, pbase: 0x%lx\n", __func__, ref_paddr, pbase);
|
||||
|
||||
paddr = ref_paddr;
|
||||
for (i = 0UL; i < PTRS_PER_PTE; i++) {
|
||||
@ -92,7 +92,7 @@ static void modify_or_del_pte(const uint64_t *pde, uint64_t vaddr_start, uint64_
|
||||
uint64_t vaddr = vaddr_start;
|
||||
uint64_t index = pte_index(vaddr);
|
||||
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, vaddr: [0x%llx - 0x%llx]\n", __func__, vaddr, vaddr_end);
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, vaddr: [0x%lx - 0x%lx]\n", __func__, vaddr, vaddr_end);
|
||||
for (; index < PTRS_PER_PTE; index++) {
|
||||
uint64_t *pte = pt_page + index;
|
||||
|
||||
@ -102,7 +102,7 @@ static void modify_or_del_pte(const uint64_t *pde, uint64_t vaddr_start, uint64_
|
||||
* is present or not.
|
||||
*/
|
||||
if ((type == MR_MODIFY) && (vaddr >= MEM_1M)) {
|
||||
pr_warn("%s, vaddr: 0x%llx pte is not present.\n", __func__, vaddr);
|
||||
pr_warn("%s, vaddr: 0x%lx pte is not present.\n", __func__, vaddr);
|
||||
}
|
||||
} else {
|
||||
local_modify_or_del_pte(pte, prot_set, prot_clr, type, mem_ops);
|
||||
@ -129,14 +129,14 @@ static void modify_or_del_pde(const uint64_t *pdpte, uint64_t vaddr_start, uint6
|
||||
uint64_t vaddr = vaddr_start;
|
||||
uint64_t index = pde_index(vaddr);
|
||||
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, vaddr: [0x%llx - 0x%llx]\n", __func__, vaddr, vaddr_end);
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, vaddr: [0x%lx - 0x%lx]\n", __func__, vaddr, vaddr_end);
|
||||
for (; index < PTRS_PER_PDE; index++) {
|
||||
uint64_t *pde = pd_page + index;
|
||||
uint64_t vaddr_next = (vaddr & PDE_MASK) + PDE_SIZE;
|
||||
|
||||
if (mem_ops->pgentry_present(*pde) == 0UL) {
|
||||
if (type == MR_MODIFY) {
|
||||
pr_warn("%s, addr: 0x%llx pde is not present.\n", __func__, vaddr);
|
||||
pr_warn("%s, addr: 0x%lx pde is not present.\n", __func__, vaddr);
|
||||
}
|
||||
} else {
|
||||
if (pde_large(*pde) != 0UL) {
|
||||
@ -174,14 +174,14 @@ static void modify_or_del_pdpte(const uint64_t *pml4e, uint64_t vaddr_start, uin
|
||||
uint64_t vaddr = vaddr_start;
|
||||
uint64_t index = pdpte_index(vaddr);
|
||||
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, vaddr: [0x%llx - 0x%llx]\n", __func__, vaddr, vaddr_end);
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, vaddr: [0x%lx - 0x%lx]\n", __func__, vaddr, vaddr_end);
|
||||
for (; index < PTRS_PER_PDPTE; index++) {
|
||||
uint64_t *pdpte = pdpt_page + index;
|
||||
uint64_t vaddr_next = (vaddr & PDPTE_MASK) + PDPTE_SIZE;
|
||||
|
||||
if (mem_ops->pgentry_present(*pdpte) == 0UL) {
|
||||
if (type == MR_MODIFY) {
|
||||
pr_warn("%s, vaddr: 0x%llx pdpte is not present.\n", __func__, vaddr);
|
||||
pr_warn("%s, vaddr: 0x%lx pdpte is not present.\n", __func__, vaddr);
|
||||
}
|
||||
} else {
|
||||
if (pdpte_large(*pdpte) != 0UL) {
|
||||
@ -227,7 +227,7 @@ void mmu_modify_or_del(uint64_t *pml4_page, uint64_t vaddr_base, uint64_t size,
|
||||
uint64_t *pml4e;
|
||||
|
||||
vaddr_end = vaddr + round_page_down(size);
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, vaddr: 0x%llx, size: 0x%llx\n",
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, vaddr: 0x%lx, size: 0x%lx\n",
|
||||
__func__, vaddr, size);
|
||||
|
||||
while (vaddr < vaddr_end) {
|
||||
@ -254,13 +254,13 @@ static void add_pte(const uint64_t *pde, uint64_t paddr_start, uint64_t vaddr_st
|
||||
uint64_t paddr = paddr_start;
|
||||
uint64_t index = pte_index(vaddr);
|
||||
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, paddr: 0x%llx, vaddr: [0x%llx - 0x%llx]\n",
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, paddr: 0x%lx, vaddr: [0x%lx - 0x%lx]\n",
|
||||
__func__, paddr, vaddr_start, vaddr_end);
|
||||
for (; index < PTRS_PER_PTE; index++) {
|
||||
uint64_t *pte = pt_page + index;
|
||||
|
||||
if (mem_ops->pgentry_present(*pte) != 0UL) {
|
||||
pr_fatal("%s, pte 0x%llx is already present!\n", __func__, vaddr);
|
||||
pr_fatal("%s, pte 0x%lx is already present!\n", __func__, vaddr);
|
||||
} else {
|
||||
set_pgentry(pte, paddr | prot, mem_ops);
|
||||
paddr += PTE_SIZE;
|
||||
@ -285,14 +285,14 @@ static void add_pde(const uint64_t *pdpte, uint64_t paddr_start, uint64_t vaddr_
|
||||
uint64_t paddr = paddr_start;
|
||||
uint64_t index = pde_index(vaddr);
|
||||
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, paddr: 0x%llx, vaddr: [0x%llx - 0x%llx]\n",
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, paddr: 0x%lx, vaddr: [0x%lx - 0x%lx]\n",
|
||||
__func__, paddr, vaddr, vaddr_end);
|
||||
for (; index < PTRS_PER_PDE; index++) {
|
||||
uint64_t *pde = pd_page + index;
|
||||
uint64_t vaddr_next = (vaddr & PDE_MASK) + PDE_SIZE;
|
||||
|
||||
if (pde_large(*pde) != 0UL) {
|
||||
pr_fatal("%s, pde 0x%llx is already present!\n", __func__, vaddr);
|
||||
pr_fatal("%s, pde 0x%lx is already present!\n", __func__, vaddr);
|
||||
} else {
|
||||
if (mem_ops->pgentry_present(*pde) == 0UL) {
|
||||
if (mem_aligned_check(paddr, PDE_SIZE) &&
|
||||
@ -332,13 +332,13 @@ static void add_pdpte(const uint64_t *pml4e, uint64_t paddr_start, uint64_t vadd
|
||||
uint64_t paddr = paddr_start;
|
||||
uint64_t index = pdpte_index(vaddr);
|
||||
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, paddr: 0x%llx, vaddr: [0x%llx - 0x%llx]\n", __func__, paddr, vaddr, vaddr_end);
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, paddr: 0x%lx, vaddr: [0x%lx - 0x%lx]\n", __func__, paddr, vaddr, vaddr_end);
|
||||
for (; index < PTRS_PER_PDPTE; index++) {
|
||||
uint64_t *pdpte = pdpt_page + index;
|
||||
uint64_t vaddr_next = (vaddr & PDPTE_MASK) + PDPTE_SIZE;
|
||||
|
||||
if (pdpte_large(*pdpte) != 0UL) {
|
||||
pr_fatal("%s, pdpte 0x%llx is already present!\n", __func__, vaddr);
|
||||
pr_fatal("%s, pdpte 0x%lx is already present!\n", __func__, vaddr);
|
||||
} else {
|
||||
if (mem_ops->pgentry_present(*pdpte) == 0UL) {
|
||||
if (mem_aligned_check(paddr, PDPTE_SIZE) &&
|
||||
@ -378,7 +378,7 @@ void mmu_add(uint64_t *pml4_page, uint64_t paddr_base, uint64_t vaddr_base, uint
|
||||
uint64_t paddr;
|
||||
uint64_t *pml4e;
|
||||
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, paddr 0x%llx, vaddr 0x%llx, size 0x%llx\n", __func__, paddr_base, vaddr_base, size);
|
||||
dev_dbg(ACRN_DBG_MMU, "%s, paddr 0x%lx, vaddr 0x%lx, size 0x%lx\n", __func__, paddr_base, vaddr_base, size);
|
||||
|
||||
/* align address to page size*/
|
||||
vaddr = round_page_up(vaddr_base);
|
||||
|
||||
@ -109,7 +109,7 @@ uint64_t prepare_trampoline(void)
|
||||
size = (uint64_t)(&ld_trampoline_end - &ld_trampoline_start);
|
||||
dest_pa = get_ap_trampoline_buf();
|
||||
|
||||
pr_dbg("trampoline code: %llx size %x", dest_pa, size);
|
||||
pr_dbg("trampoline code: %lx size %x", dest_pa, size);
|
||||
|
||||
/* Copy segment for AP initialization code below 1MB */
|
||||
(void)memcpy_s(hpa2hva(dest_pa), (size_t)size, &ld_trampoline_load,
|
||||
|
||||
@ -464,7 +464,7 @@ static int32_t dmar_register_hrhd(struct dmar_drhd_rt *dmar_unit)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
|
||||
dev_dbg(ACRN_DBG_IOMMU, "Register dmar uint [%d] @0x%llx", dmar_unit->index, dmar_unit->drhd->reg_base_addr);
|
||||
dev_dbg(ACRN_DBG_IOMMU, "Register dmar uint [%d] @0x%lx", dmar_unit->index, dmar_unit->drhd->reg_base_addr);
|
||||
|
||||
spinlock_init(&dmar_unit->lock);
|
||||
|
||||
@ -479,7 +479,7 @@ static int32_t dmar_register_hrhd(struct dmar_drhd_rt *dmar_unit)
|
||||
dmar_unit->ecap_iotlb_offset = iommu_ecap_iro(dmar_unit->ecap) * 16U;
|
||||
|
||||
#if DBG_IOMMU
|
||||
pr_info("version:0x%x, cap:0x%llx, ecap:0x%llx",
|
||||
pr_info("version:0x%x, cap:0x%lx, ecap:0x%lx",
|
||||
iommu_read32(dmar_unit, DMAR_VER_REG), dmar_unit->cap, dmar_unit->ecap);
|
||||
pr_info("sagaw:0x%x, msagaw:0x%x, iotlb offset 0x%x",
|
||||
iommu_cap_sagaw(dmar_unit->cap), dmar_unit->cap_msagaw, dmar_unit->ecap_iotlb_offset);
|
||||
@ -875,7 +875,7 @@ static void fault_record_analysis(__unused uint64_t low, uint64_t high)
|
||||
if (!dma_frcd_up_f(high)) {
|
||||
dmar_bdf.value = dma_frcd_up_sid(high);
|
||||
/* currently skip PASID related parsing */
|
||||
pr_info("%s, Reason: 0x%x, SID: %x.%x.%x @0x%llx",
|
||||
pr_info("%s, Reason: 0x%x, SID: %x.%x.%x @0x%lx",
|
||||
(dma_frcd_up_t(high) != 0U) ? "Read/Atomic" : "Write", dma_frcd_up_fr(high),
|
||||
dmar_bdf.bits.b, dmar_bdf.bits.d, dmar_bdf.bits.f, low);
|
||||
#if DBG_IOMMU
|
||||
@ -916,7 +916,7 @@ static void dmar_fault_handler(uint32_t irq, void *data)
|
||||
fault_record.lo_64 = iommu_read64(dmar_unit, record_reg_offset);
|
||||
fault_record.hi_64 = iommu_read64(dmar_unit, record_reg_offset + 8U);
|
||||
|
||||
dev_dbg(ACRN_DBG_IOMMU, "%s: record[%d] @0x%x: 0x%llx, 0x%llx",
|
||||
dev_dbg(ACRN_DBG_IOMMU, "%s: record[%d] @0x%x: 0x%lx, 0x%lx",
|
||||
__func__, index, record_reg_offset, fault_record.lo_64, fault_record.hi_64);
|
||||
|
||||
fault_record_analysis(fault_record.lo_64, fault_record.hi_64);
|
||||
@ -1117,7 +1117,7 @@ static int32_t add_iommu_device(struct iommu_domain *domain, uint16_t segment, u
|
||||
ret = -EINVAL;
|
||||
} else if (dmar_get_bitslice(context_entry->lo_64, CTX_ENTRY_LOWER_P_MASK, CTX_ENTRY_LOWER_P_POS) != 0UL) {
|
||||
/* the context entry should not be present */
|
||||
pr_err("%s: context entry@0x%llx (Lower:%x) ", __func__, context_entry, context_entry->lo_64);
|
||||
pr_err("%s: context entry@0x%lx (Lower:%x) ", __func__, context_entry, context_entry->lo_64);
|
||||
pr_err("already present for %x:%x.%x", bus, sid.bits.d, sid.bits.f);
|
||||
ret = -EBUSY;
|
||||
} else {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user