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acrn-config: enable CAT for industry scenario on APL-UP2 by default

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Tracked-On: #4566
Signed-off-by: Yan, Like <like.yan@intel.com>
Signed-off-by: Liu, Wei <weix.w.liu@intel.com>
This commit is contained in:
Yan, Like
2020-03-24 16:47:41 +08:00
committed by wenlingz
parent 0b384b7284
commit e66c27df77
37 changed files with 327 additions and 110 deletions
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8
misc/acrn-config/xmls/config-xmls/apl-mrb/logical_partition.xml
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@@ -10,7 +10,9 @@
<pcpu_id>0</pcpu_id>
<pcpu_id>2</pcpu_id>
</vcpu_affinity>
<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
<clos configurable="0" desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">>
<vcpu_clos>0</vcpu_clos>
</clos>
<epc_section desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>
<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
@@ -59,7 +61,9 @@
<pcpu_id>1</pcpu_id>
<pcpu_id>3</pcpu_id>
</vcpu_affinity>
<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
<clos configurable="0" desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
<vcpu_clos>0</vcpu_clos>
</clos>
<epc_section desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>
<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>