github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2026-06-09 02:24:45 +00:00
Code Issues Projects Releases Wiki Activity

acrn-config: enable CAT for industry scenario on APL-UP2 by default

Browse Source 
Tracked-On: #4566
Signed-off-by: Yan, Like <like.yan@intel.com>
Signed-off-by: Liu, Wei <weix.w.liu@intel.com>
This commit is contained in:
Yan, Like
2020-03-24 16:47:41 +08:00
committed by wenlingz
parent 0b384b7284
commit e66c27df77
37 changed files with 327 additions and 110 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
misc/acrn-config/xmls/config-xmls/apl-up2-n3350/logical_partition.xml
View File

@@ -10,7 +10,9 @@
<vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
<pcpu_id>0</pcpu_id>
</vcpu_affinity>
<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
<clos configurable="0" desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
<vcpu_clos>0</vcpu_clos>
</clos>
<epc_section desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>
<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>
@@ -58,7 +60,9 @@
<vcpu_affinity desc="vCPU affinity map. Each vCPU will pin to the selected pCPU ID. Please make sure each vCPU pin to different pCPU.">
<pcpu_id>1</pcpu_id>
</vcpu_affinity>
<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">0</clos>
<clos configurable="0" desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
<vcpu_clos>0</vcpu_clos>
</clos>
<epc_section desc="epc section">
<base desc="SGX EPC section base, must be page aligned">0</base>
<size desc="SGX EPC section size in Bytes, must be page aligned">0</size>