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HV: Avoiding the chained assignment
To follow the Misra C standard, doing one assignment per line to make code is clearly readable and reduces the confusion of its intetion or typo. Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
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@ -164,7 +164,8 @@ int set_vcpuid_entries(struct vm *vm)
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result = set_vcpuid_entry(vm, &entry);
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result = set_vcpuid_entry(vm, &entry);
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if (result != 0)
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if (result != 0)
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return result;
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return result;
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vm->vcpuid_level = limit = entry.eax;
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limit = entry.eax;
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vm->vcpuid_level = limit;
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for (i = 1U; i <= limit; i++) {
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for (i = 1U; i <= limit; i++) {
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/* cpuid 1/0xb is percpu related */
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/* cpuid 1/0xb is percpu related */
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@ -235,7 +236,8 @@ int set_vcpuid_entries(struct vm *vm)
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if (result != 0)
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if (result != 0)
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return result;
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return result;
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vm->vcpuid_xlevel = limit = entry.eax;
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limit = entry.eax;
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vm->vcpuid_xlevel = limit;
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for (i = 0x80000001U; i <= limit; i++) {
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for (i = 0x80000001U; i <= limit; i++) {
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init_vcpuid_entry(vm, i, 0U, 0U, &entry);
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init_vcpuid_entry(vm, i, 0U, 0U, &entry);
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result = set_vcpuid_entry(vm, &entry);
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result = set_vcpuid_entry(vm, &entry);
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@ -49,8 +49,8 @@ void acrn_update_ucode(struct vcpu *vcpu, uint64_t v)
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data_page_num =
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data_page_num =
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(data_size + CPU_PAGE_SIZE - 1) >> CPU_PAGE_SHIFT;
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(data_size + CPU_PAGE_SIZE - 1) >> CPU_PAGE_SHIFT;
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ptr = ucode_ptr = alloc_pages(data_page_num);
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ucode_ptr = alloc_pages(data_page_num);
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if (ptr == NULL)
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if (ucode_ptr == NULL)
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return;
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return;
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err_code = 0U;
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err_code = 0U;
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@ -62,7 +62,7 @@ void acrn_update_ucode(struct vcpu *vcpu, uint64_t v)
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return;
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return;
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msr_write(MSR_IA32_BIOS_UPDT_TRIG,
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msr_write(MSR_IA32_BIOS_UPDT_TRIG,
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(uint64_t)ptr + sizeof(struct ucode_header));
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(uint64_t)ucode_ptr + sizeof(struct ucode_header));
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get_microcode_version();
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get_microcode_version();
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free(ucode_ptr);
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free(ucode_ptr);
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@ -327,11 +327,11 @@ vioapic_write(struct vioapic *vioapic, uint32_t addr, uint32_t data)
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else
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else
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lshift = 0;
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lshift = 0;
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last = new = vioapic->rtbl[pin].reg;
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last = vioapic->rtbl[pin].reg;
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data64 = (uint64_t)data << lshift;
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data64 = (uint64_t)data << lshift;
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mask64 = (uint64_t)0xffffffff << lshift;
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mask64 = (uint64_t)0xffffffff << lshift;
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new &= ~mask64 | RTBL_RO_BITS;
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new = last & (~mask64 | RTBL_RO_BITS);
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new |= data64 & ~RTBL_RO_BITS;
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new |= data64 & ~RTBL_RO_BITS;
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changed = last ^ new;
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changed = last ^ new;
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@ -101,7 +101,8 @@ int create_vm(struct vm_description *vm_desc, struct vm **rtn_vm)
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for (id = 0U; id < (size_t)(sizeof(long) * 8U); id++)
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for (id = 0U; id < (size_t)(sizeof(long) * 8U); id++)
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if (!bitmap_test_and_set(id, &vmid_bitmap))
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if (!bitmap_test_and_set(id, &vmid_bitmap))
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break;
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break;
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vm->attr.id = vm->attr.boot_idx = id;
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vm->attr.id = id;
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vm->attr.boot_idx = id;
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atomic_store(&vm->hw.created_vcpus, 0);
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atomic_store(&vm->hw.created_vcpus, 0);
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@ -772,12 +772,20 @@ static void init_guest_state(struct vcpu *vcpu)
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/***************************************************/
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/***************************************************/
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data32_idx = 0x10;
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data32_idx = 0x10;
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if (vcpu_mode == CPU_MODE_REAL) {
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if (vcpu_mode == CPU_MODE_REAL) {
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es = ss = ds = fs = gs = data32_idx;
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es = data32_idx;
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ss = data32_idx;
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ds = data32_idx;
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fs = data32_idx;
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gs = data32_idx;
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limit = 0xffff;
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limit = 0xffff;
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} else if (vcpu_mode == CPU_MODE_PROTECTED) {
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} else if (vcpu_mode == CPU_MODE_PROTECTED) {
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/* Linear data segment in guest init gdt */
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/* Linear data segment in guest init gdt */
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es = ss = ds = fs = gs = 0x18;
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es = 0x18;
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ss = 0x18;
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ds = 0x18;
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fs = 0x18;
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gs = 0x18;
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limit = 0xffffffffU;
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limit = 0xffffffffU;
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} else if (vcpu_mode == CPU_MODE_64BIT) {
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} else if (vcpu_mode == CPU_MODE_64BIT) {
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asm volatile ("movw %%es, %%ax":"=a" (es));
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asm volatile ("movw %%es, %%ax":"=a" (es));
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@ -101,7 +101,8 @@ static void _get_req_info_(struct vhm_request *req, int *id, char *type,
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char *state, char *dir, long *addr, long *val)
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char *state, char *dir, long *addr, long *val)
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{
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{
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(void)strcpy_s(dir, 16, "NONE");
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(void)strcpy_s(dir, 16, "NONE");
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*addr = *val = 0;
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*addr = 0;
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*val = 0;
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*id = req->client;
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*id = req->client;
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switch (req->type) {
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switch (req->type) {
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